diff options
| author | John Zhao <john.zhao@intel.com> | 2020-09-22 09:03:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-28 09:29:03 +0000 |
| commit | d51449d017410fedb55e93f71fb322749ba888b5 (patch) | |
| tree | 332ce5e92dcc05057bcd197994b986a27bf9060b /src/soc/intel | |
| parent | 06b35e5cede9c20e9af5c9f1c3f6f93745106749 (diff) | |
soc/intel/xeon_sp: Improve performance efficiencies
Coverity detects performance inefficiencies as IIO_RESOUCE_INSTANCE
structure (size 623 bytes) is PASS_BY_VALUE. Fix it with
PASS_BY_REFERENCE.
Found-by: Coverity CID 1432759
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/acpi.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index cd497c597b..1b6f1a3958 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -605,16 +605,16 @@ static int get_stack_for_port(int port) * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, bool is_atsr, bool *first) { if (get_stack_for_port(port) != stack) return 0; - const uint32_t bus = iio_resource.StackRes[stack].BusBase; - const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + const uint32_t bus = iio_resource->StackRes[stack].BusBase; + const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -703,8 +703,8 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, // Add PCIe Ports if (socket != 0 || stack != CSTACK) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; + const IIO_RESOURCE_INSTANCE *iio_resource = + &hob->PlatformData.IIO_resource[socket]; for (int p = PORT_0; p < MAX_PORTS; ++p) current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, iio_resource, pcie_seg, false, NULL); @@ -748,12 +748,12 @@ static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; unsigned long tmp = current; bool first = true; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; + const IIO_RESOURCE_INSTANCE *iio_resource = + &hob->PlatformData.IIO_resource[socket]; for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = iio_resource.StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + uint32_t bus = iio_resource->StackRes[stack].BusBase; + uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress; if (!vtd_base) continue; uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); @@ -821,10 +821,10 @@ static unsigned long acpi_create_rhsa(unsigned long current) assert(hob != NULL && hob_size != 0); for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; + IIO_RESOURCE_INSTANCE *iio_resource = + &hob->PlatformData.IIO_resource[socket]; for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress; if (!vtd_base) continue; |