diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-09-07 16:37:21 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-12 12:24:09 +0000 |
| commit | cf46099979155659d9c5e781906764887c9c48c6 (patch) | |
| tree | 0cb78a95c5447ef87bb4c9edd5de2066f1689cc6 /src/soc/intel | |
| parent | ff7725e74281a4ae9c776525891d45233599bce4 (diff) | |
soc/intel/adl: Disable D3cold when legacy S3 is enabled
D3Cold isn't supported in S3.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I072f47737ef38c44b6a676019e9a73868ff17e5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67413
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index dd17e33d36..79958064e3 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -646,7 +646,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable; + s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable; s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |