acpi/gnvs.c: Drop unused pointer to the cbmem console

Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>

12 files changed, 12 insertions, 12 deletions

diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index a56d2e106c..ad5119cd39 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -14,7 +14,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,      // 0x02 - LID State
 	,	8,      // 0x03 - AC Power State
 	DPTE,	8,      // 0x04 - Enable DPTF
-	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
+	,	32,     // 0x05 - 0x08 - coreboot Memory Console
 	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
 	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
 	NHLA,	64,     // 0x19 - 0x20 - NHLT Address
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 95d9ab43a3..c1f575b65e 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -18,7 +18,7 @@ struct __packed global_nvs {
 	uint8_t		lids; /* 0x02 - LID State */
 	uint8_t		unused_was_pwrs; /* 0x03 - AC Power State */
 	uint8_t		dpte; /* 0x04 - Enable DPTF */
-	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
 	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 1654cd876f..0f6d480f4c 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -40,5 +40,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	Offset (0x30),
 	,	 32,	/* 0x30 - CBMEM TOC */
 	,	 32,	/* 0x34 - Top of Low Memory */
-	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
+	,	 32,	/* 0x38 - coreboot mem console pointer */
 }
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 35308cd352..56527617f8 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -42,7 +42,7 @@ struct __packed global_nvs {
 	/* Base Addresses */
 	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
-	u32	cbmc; /* 0x38 - coreboot memconsole */
+	u32	unused_was_cbmc; /* 0x38 - coreboot memconsole */
 };
 
 #endif /* _BAYTRAIL_NVS_H_ */
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index c0839e6e88..fb28acceb0 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -41,5 +41,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	Offset (0x30),
 	,	 32,	/* 0x30 - CBMEM TOC */
 	,	 32,	/* 0x34 - Top of Low Memory */
-	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
+	,	 32,	/* 0x38 - coreboot mem console pointer */
 }
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 59c6052abe..2351978288 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -43,7 +43,7 @@ struct __packed global_nvs {
 	/* Base Addresses */
 	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
-	u32	cbmc; /* 0x38 - coreboot memconsole */
+	u32	unused_was_cbmc; /* 0x38 - coreboot memconsole */
 };
 
 #endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index c57a698d6d..f627c8076d 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -31,7 +31,7 @@ struct __packed global_nvs {
 	u8	lids; /* 0x16 - LID State */
 	u8	unused_was_pwrs; /* 0x17 - AC Power State */
 	u32	obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
-	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
+	u32	unused_was_cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
 };
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
index bfc22fb315..67fdbee91d 100644
--- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
@@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,	// 0x16 - LID State
 	,	8,	// 0x17 - AC Power State
 	,	32,	// 0x18 - 0x1b - CBMEM TOC
-	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
+	,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
 }
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index 2c72b7d2ac..adda519e90 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -12,7 +12,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TLVL,	8,	// 0x05 - Throttle Level Limit
 	LIDS,	8,	// 0x06 - LID State
 	,	8,	// 0x07 - AC Power State
-	CBMC,	32,	// 0x08 - 0x0b AC Power State
+	,	32,	// 0x08 - 0x0b AC Power State
 	PM1I,	64,	// 0x0c - 0x13 PM1 wake status bit
 	GPEI,	64,	// 0x14 - 0x17 GPE wake status bit
 	DPTE,	8,	// 0x1c - Enable DPTF
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 4fc5b4c4c8..071be665ea 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -14,7 +14,7 @@ struct __packed global_nvs {
 	u8	tlvl; /* 0x05 - Throttle Level Limit */
 	u8	lids; /* 0x06 - LID State */
 	u8	unused_was_pwrs; /* 0x07 - AC Power State */
-	u32	cbmc; /* 0x08 - 0xb coreboot Memory Console */
+	u32	unused_was_cbmc; /* 0x08 - 0xb coreboot Memory Console */
 	u64	pm1i; /* 0x0c - 0x13 PM1 wake status bit */
 	u64	gpei; /* 0x14 - 0x1b GPE wake status bit */
 	u8	dpte; /* 0x1c - Enable DPTF */
diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
index 3100c1f848..9f19d257fe 100644
--- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl
+++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
@@ -38,7 +38,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	Offset (0x30),
 	,	 32,	// 0x30 - CBMEM TOC
 	TOLM,	 32,	// 0x34 - Top of Low Memory
-	CBMC,	 32,	// 0x38 - coreboot mem console pointer
+	,	 32,	// 0x38 - coreboot mem console pointer
 	MMOB,	 32,	// 0x3c - MMIO Base Low Base
 	MMOL,	 32,	// 0x40 - MMIO Base Low Limit
 	MMHB,	 64,	// 0x44 - MMIO Base High Base
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
index 5fa235e84f..65de751e2a 100644
--- a/src/soc/intel/denverton_ns/include/soc/nvs.h
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -38,7 +38,7 @@ struct __packed global_nvs {
 	/* Base Addresses */
 	u32 obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32 tolm;	  /* 0x34 - Top of Low Memory */
-	u32 cbmc;	  /* 0x38 - coreboot memconsole */
+	u32 unused_was_cbmc;	  /* 0x38 - coreboot memconsole */
 	u32 mmiob;	 /* 0x3c - MMIO Base Low */
 	u32 mmiol;	 /* 0x40 - MMIO Base Limit */
 	u64 mmiohb;	/* 0x44 - MMIO Base High */