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authorElyes HAOUAS <ehaouas@noos.fr>2020-06-27 07:17:16 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-30 05:58:08 +0000
commitbda27cd336a784d6ac55b2eb8af2635b26545fc4 (patch)
tree0c11a4b0c20cb24d3fbc49f7bc66e07e5e855b6f /src/soc/intel
parente8d230d65d9cba20da77d0c5d200edf40286e09d (diff)
src: Remove whitespaces before tabs
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/acpi/scs.asl2
-rw-r--r--src/soc/intel/common/acpi/lpit.asl2
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_dma.asl4
-rw-r--r--src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl2
4 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index ae0afc8123..8e1de1e0e1 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -82,7 +82,7 @@ Scope (\_SB.PCI0) {
* containing one bit for each function index, starting
* with zero.
* Bit 0 - Indicates whether there is support for any
- * functions other than function 0
+ * functions other than function 0
* Bit 1 - Indicates support to clear power control
* register
* Bit 2 - Indicates support to set power control
diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl
index b81275e224..348ae5612c 100644
--- a/src/soc/intel/common/acpi/lpit.asl
+++ b/src/soc/intel/common/acpi/lpit.asl
@@ -69,7 +69,7 @@ Scope(\_SB)
/*
* Save the current PM bits then
* enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
- */
+ */
If (CondRefOf (\_SB.PCI0.EGPM))
{
\_SB.PCI0.EGPM ()
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index 8eab92f22e..3d44d925df 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -56,7 +56,7 @@ Method (_PR3)
*/
Method (D3CX, 0, Serialized)
{
- DD3E = 0 /* Disable DMA RTD3 */
+ DD3E = 0 /* Disable DMA RTD3 */
STAT = 0x1
}
@@ -65,7 +65,7 @@ Method (D3CX, 0, Serialized)
*/
Method (D3CE, 0, Serialized)
{
- DD3E = 1 /* Enable DMA RTD3 */
+ DD3E = 1 /* Enable DMA RTD3 */
STAT = 0
}
diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl
index d83bf263f0..0505152a29 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl
+++ b/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl
@@ -6,7 +6,7 @@
* The mapping fields ae Address, Pin, Source, Source Index.
*/
-#define GEN_PCIE_LEGACY_IRQ() \
+#define GEN_PCIE_LEGACY_IRQ() \
Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \
Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \