diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-12-20 09:17:18 -0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-12-22 12:27:09 +0000 |
| commit | ba07f95992d4a430383696a4654ad222178df242 (patch) | |
| tree | 291d561111feb7128494bcaee320d568479ed2b8 /src/soc/intel | |
| parent | ba757a71fef07d876f06a35b6374bcf00f40ded6 (diff) | |
soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if
TME is enabled but Meteor Lake SoC physical address size is always
42.
BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP
Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 8b2a6a22d0..756d4990ec 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -463,4 +463,8 @@ config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE Enable the FSP-M Sign-of-Life feature to display a configurable text message on screen during memory training and CSME update. + +config SOC_PHYSICAL_ADDRESS_WIDTH + default 42 + endif |