diff options
author | Morgan Jang <Morgan_Jang@wiwynn.com> | 2020-05-25 12:23:59 +0800 |
---|---|---|
committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-07-16 13:07:31 +0000 |
commit | b29d16fc8a1e15a9a5e7f5b389019b7593d42d02 (patch) | |
tree | c4b732fc6dd19f0a9b67f48eda158bc22b456572 /src/soc/intel | |
parent | b8d0d089b307a8e40f12af82d0191d52f8752b37 (diff) |
mb/ocp/deltalake: Config PCH PCIe ports in devicetree
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 61e806e473..e46f34f653 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -7,10 +7,35 @@ #include <soc/irq.h> #include <stdint.h> +#define MAX_PCH_PCIE_PORT 20 + +/** + UPD_PCH_PCIE_PORT: + ForceEnable - Enable/Disable PCH PCIe port + PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set +**/ +struct pch_pcie_port { + uint8_t ForceEnable; + uint8_t PortLinkSpeed; +}; + +/** + PCIe Link Speed Selection + **/ +typedef enum { + PcieAuto = 0, + PcieGen1, + PcieGen2, + PcieGen3 +} pcie_link_speed; + struct soc_intel_xeon_sp_cpx_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Struct for configuring PCH PCIe port */ + struct pch_pcie_port pch_pci_port[MAX_PCH_PCIE_PORT]; + /** * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. |