diff options
| author | MAULIK V VAGHELA <maulik.v.vaghela@intel.com> | 2021-08-06 18:52:25 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-10 21:19:38 +0000 |
| commit | b2513faab2ebf48214d6d9669b85760650b96f83 (patch) | |
| tree | 969aefe87b5b4f4fdebd80baf507403ea7cad1ee /src/soc/intel | |
| parent | 563a6cc6f2690f2594df51d8d16b3e9f4ef5ca8d (diff) | |
mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 532ec38395..2d5c54e4ae 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -1,5 +1,7 @@ chip soc/intel/alderlake + device cpu_cluster 0 on end + register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, |