diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-07-26 12:54:57 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-07-28 11:13:34 +0000 |
| commit | a459d360e45ac19295ab01a5f5df21e130dbe949 (patch) | |
| tree | fcad167c95199c3933d6a0d576adb997651b3450 /src/soc/intel | |
| parent | 2ba4bfef7ed31ff2950ecd6c7269d4148d652764 (diff) | |
soc/intel/meteorlake: Fix GPIO reset mapping as per GPIO BWG
This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG.
As per GPIO BWG, there are four GPIO reset types in Meteor Lake as
below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- Global Reset for GPP - (Value 11)
Also, dropped the need for having dedicated reset type for GPIO
community 3. As per the MTL EDS, all GPIO communities have the same
reset type.
BUG=b:213293047
TEST=Able to build and boot Google/Rex without below error msg.
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping
not found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id7ea16d89b6f01b00a7b7c52945f6e01e8db6cbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Will Kim <norwayforest92@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/meteorlake/gpio.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/soc/intel/meteorlake/gpio.c b/src/soc/intel/meteorlake/gpio.c index 83c6d840ba..74b0f6b680 100644 --- a/src/soc/intel/meteorlake/gpio.c +++ b/src/soc/intel/meteorlake/gpio.c @@ -8,15 +8,10 @@ #define DEFAULT_VW_BASE 0x10 static const struct reset_mapping rst_map[] = { - { .logical = PAD_RESET(RSMRST), .chipset = 0U << 30 }, - { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, - { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, -}; -static const struct reset_mapping rst_map_com3[] = { { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, - { .logical = PAD_RESET(RSMRST), .chipset = 3U << 30 }, + { .logical = PAD_RESET(GLBRST), .chipset = 3U << 30 }, }; /* @@ -147,8 +142,8 @@ static const struct pad_community mtl_communities[] = { .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_HFSPI0VG3", .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map_com3, - .num_reset_vals = ARRAY_SIZE(rst_map_com3), + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), .groups = mtl_community3_groups, .num_groups = ARRAY_SIZE(mtl_community3_groups), .vw_base = DEFAULT_VW_BASE, |