soc/intel/broadwell: Clean up the bootflow

Call the raminit from a common location instead of from the mainboard
specific code.

Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 23 insertions, 26 deletions

diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index 46f29d62df..d65692ae23 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -27,8 +27,8 @@ struct romstage_params {
 	struct pei_data pei_data;
 };
 
-void mainboard_romstage_entry(struct romstage_params *params);
-void romstage_common(struct romstage_params *params);
+void mainboard_pre_raminit(struct romstage_params *params);
+void mainboard_post_raminit(struct romstage_params *params);
 
 void raminit(struct pei_data *pei_data);
 
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 2a3ac8b8e6..acbca14a88 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -103,47 +103,44 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
 	/* Initialize GPIOs */
 	init_gpios(mainboard_gpio_config);
 
-	/* Call into mainboard. */
-	mainboard_romstage_entry(&rp);
+	/* Fill in mainboard pei_date. */
+	mainboard_pre_raminit(&rp);
 
-	platform_enter_postcar();
-}
-
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-{
-	romstage_main(base_timestamp, bist);
-}
-
-/* Entry from the mainboard. */
-void romstage_common(struct romstage_params *params)
-{
 	post_code(0x32);
 
 	timestamp_add_now(TS_BEFORE_INITRAM);
 
-	params->pei_data.boot_mode = params->power_state->prev_sleep_state;
+	rp.pei_data.boot_mode = rp.power_state->prev_sleep_state;
 
-#if CONFIG(ELOG_BOOT_COUNT)
-	if (params->power_state->prev_sleep_state != ACPI_S3)
+	if (CONFIG(ELOG_BOOT_COUNT)
+			&& rp.power_state->prev_sleep_state != ACPI_S3)
 		boot_count_increment();
-#endif
 
 	/* Print ME state before MRC */
 	intel_me_status();
 
 	/* Save ME HSIO version */
-	intel_me_hsio_version(&params->power_state->hsio_version,
-			      &params->power_state->hsio_checksum);
+	intel_me_hsio_version(&rp.power_state->hsio_version,
+			      &rp.power_state->hsio_checksum);
 
 	/* Initialize RAM */
-	raminit(&params->pei_data);
+	raminit(&rp.pei_data);
 
 	timestamp_add_now(TS_AFTER_INITRAM);
 
-	romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
+	romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3);
+
+	mainboard_post_raminit(&rp);
+
+	platform_enter_postcar();
+}
+
+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+	romstage_main(base_timestamp, bist);
 }
 
 void __weak mainboard_pre_console_init(void) {}