intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor

Remove cases of __PRE_RAM__ and other preprocessor guards.

Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

15 files changed, 20 insertions, 65 deletions

diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h
index e39758c64b..5038bf87db 100644
--- a/src/soc/intel/baytrail/include/soc/msr.h
+++ b/src/soc/intel/baytrail/include/soc/msr.h
@@ -40,5 +40,6 @@
 
 /* Read BCLK from MSR */
 unsigned bus_freq_khz(void);
+void set_max_freq(void);
 
 #endif /* _BAYTRAIL_MSR_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h
index d20859d055..f98a79b2ea 100644
--- a/src/soc/intel/baytrail/include/soc/ramstage.h
+++ b/src/soc/intel/baytrail/include/soc/ramstage.h
@@ -23,7 +23,6 @@
  * initialization, but it's after console and cbmem has been reinitialized. */
 void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
 void baytrail_init_cpus(struct device *dev);
-void set_max_freq(void);
 void southcluster_enable_dev(struct device *dev);
 #if CONFIG(HAVE_REFCODE_BLOB)
 void baytrail_run_reference_code(void);
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index 3dc24f0777..8ea2d699c7 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -35,12 +35,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state);
 void gfx_init(void);
 void tco_disable(void);
 void punit_init(void);
-void set_max_freq(void);
-
-#if CONFIG(ENABLE_BUILTIN_COM1)
 void byt_config_com1_and_enable(void);
-#else
-static inline void byt_config_com1_and_enable(void) { }
-#endif
 
 #endif /* _BAYTRAIL_ROMSTAGE_H_ */
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index cf6a856b7b..7a413d9c1d 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -36,6 +36,7 @@
 #include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
+#include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
 #include <soc/romstage.h>
@@ -131,7 +132,8 @@ static void romstage_main(uint64_t tsc)
 
 	tco_disable();
 
-	byt_config_com1_and_enable();
+	if (CONFIG(ENABLE_BUILTIN_COM1))
+		byt_config_com1_and_enable();
 
 	console_init();
 
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c
index f9c3014273..5b2d13599d 100644
--- a/src/soc/intel/baytrail/tsc_freq.c
+++ b/src/soc/intel/baytrail/tsc_freq.c
@@ -47,13 +47,6 @@ unsigned long tsc_freq_mhz(void)
 	return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
 }
 
-#if !defined(__SMM__)
-#if !defined(__PRE_RAM__)
-#include <soc/ramstage.h>
-#else
-#include <soc/romstage.h>
-#endif
-
 void set_max_freq(void)
 {
 	msr_t perf_ctl;
@@ -76,5 +69,3 @@ void set_max_freq(void)
 
 	wrmsr(IA32_PERF_CTL, perf_ctl);
 }
-
-#endif /* __SMM__ */
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 7fe8f70581..0c86ce394a 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -29,6 +29,7 @@
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
 
+#include <soc/baytrail.h>
 #include <soc/msr.h>
 #include <soc/pattrs.h>
 #include <soc/ramstage.h>
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index f11b206ed4..48f0cdd755 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -31,12 +31,6 @@
 #include <soc/iomap.h>
 #include <soc/smm.h>
 
-#ifdef __PRE_RAM__
-#include <soc/romstage.h>
-#endif
-
-#ifdef __PRE_RAM__
-
 /* Copy the default UPD region and settings to a buffer for modification */
 static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION   *UpdData)
 {
@@ -307,10 +301,9 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
 	ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
 	pFspInitParams->NvsBufferPtr = NULL;
 
-#if CONFIG(ENABLE_MRC_CACHE)
 	/* Find the fastboot cache that was saved in the ROM */
-	pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
-#endif
+	if (CONFIG(ENABLE_MRC_CACHE))
+		pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
 
 	if (prev_sleep_state == ACPI_S3) {
 		/* S3 resume */
@@ -335,5 +328,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
 
 	return;
 }
-
-#endif	/* __PRE_RAM__ */
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index 6da1258bf3..3e2499accd 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -29,13 +29,11 @@
  *   PCU iLB GPIO CFIO_SCORE Address Map
  *   PCU iLB GPIO CFIO_SSUS Address Map
  */
-#ifndef __PRE_RAM__
 static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
 	{ 19, 18, 17, 20, 21, 22, 24, 25,	/* [ 0: 7] */
 	  23, 16, 14, 15, 12, 26, 27,  1,	/* [ 8:15] */
 	   4,  8, 11,  0,  3,  6, 10, 13,	/* [16:23] */
 	   2,  5,  9 };				/* [24:26] */
-#endif
 
 static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
 	{  85,  89, 93,  96, 99, 102,  98, 101,	/* [ 0:  7] */
@@ -61,8 +59,6 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
 	  52, 53, 59, 40 };			/* [40:43] */
 
 
-#ifndef __PRE_RAM__
-
 /* GPIO bank descriptions */
 static const struct gpio_bank gpncore_bank = {
 	.gpio_count = GPNCORE_COUNT,
@@ -253,7 +249,6 @@ struct soc_gpio_config* __weak mainboard_get_gpios(void)
 	printk(BIOS_DEBUG, "Default/empty GPIO config\n");
 	return NULL;
 }
-#endif /* #ifndef __PRE_RAM__ */
 
 /** \brief returns the input / output value from an SCORE GPIO
  *
diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
index 34831b13bb..3a2fcaa635 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
@@ -35,23 +35,24 @@
 #else
 #define DEFAULT_RCBA		0xfed1c000
 #endif
-/* Everything below this line is ignored in the DSDT */
-#ifndef __ACPI__
 
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define SKPAD 0xFC
 
 /* SOC types */
 #define SOC_TYPE_BAYTRAIL	0x0F1C
 
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
 #ifndef __ASSEMBLER__
-static inline void barrier(void) { asm("" ::: "memory"); }
+#include <device/device.h>
 
-#define SKPAD 0xFC
+static inline void barrier(void) { asm("" ::: "memory"); }
 
 int bridge_silicon_revision(void);
 void rangeley_early_initialization(void);
+void set_max_freq(void);
 
-#ifndef __PRE_RAM__
 /* soc.c */
 int soc_silicon_revision(void);
 int soc_silicon_type(void);
@@ -60,8 +61,7 @@ void soc_enable(struct device *dev);
 
 void report_platform_info(void);
 
-#endif	/* __PRE_RAM__ */
 #endif	/* __ASSEMBLER__ */
-
 #endif	/* __ACPI__ */
+
 #endif
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
index 75daba540e..71c8e10446 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
@@ -283,6 +283,8 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
+uint32_t chipset_prev_sleep_state(uint32_t clear);
+
 #if CONFIG(ELOG)
 void southcluster_log_state(void);
 #else
diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h
index e8f81bb5c0..45fda9e937 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h
@@ -22,7 +22,6 @@
  * initialization, but it's after console and cbmem has been reinitialized. */
 void baytrail_init_pre_device(void);
 void baytrail_init_cpus(struct device *dev);
-void set_max_freq(void);
 void southcluster_enable_dev(struct device *dev);
 void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
 
diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h
index 5f0bd8d9c3..dce953993a 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h
@@ -17,31 +17,18 @@
 #ifndef _BAYTRAIL_ROMSTAGE_H_
 #define _BAYTRAIL_ROMSTAGE_H_
 
-#if !defined(__PRE_RAM__)
-#error "Don't include romstage.h from a ramstage compilation unit!"
-#endif
-
-void report_platform_info(void);
-
 #include <stdint.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 
 void main(FSP_INFO_HEADER *fsp_info_header);
-uint32_t chipset_prev_sleep_state(uint32_t clear);
 
 #define NUM_ROMSTAGE_TS 4
 
 void tco_disable(void);
 void punit_init(void);
-void set_max_freq(void);
 void early_mainboard_romstage_entry(void);
 void late_mainboard_romstage_entry(void);
 void get_func_disables(uint32_t *mask, uint32_t *mask2);
-
-#if CONFIG(ENABLE_BUILTIN_COM1)
 void byt_config_com1_and_enable(void);
-#else
-static inline void byt_config_com1_and_enable(void) { }
-#endif
 
 #endif /* _BAYTRAIL_ROMSTAGE_H_ */
diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c
index 98f35f06d4..2b5dad7ab7 100644
--- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c
+++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c
@@ -17,7 +17,7 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <soc/iosf.h>
-#include <soc/romstage.h>
+#include <soc/baytrail.h>
 #include <cpu/x86/msr.h>
 #include <soc/msr.h>
 #include <cpu/x86/name.h>
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 35b531a465..f347591599 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -167,7 +167,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 	tco_disable();
 
 	post_code(0x42);
-	byt_config_com1_and_enable();
+	if (CONFIG(ENABLE_BUILTIN_COM1))
+		byt_config_com1_and_enable();
 
 	post_code(0x43);
 	console_init();
diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c
index f9c3014273..6605575691 100644
--- a/src/soc/intel/fsp_baytrail/tsc_freq.c
+++ b/src/soc/intel/fsp_baytrail/tsc_freq.c
@@ -17,6 +17,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
 #include <soc/msr.h>
+#include <soc/baytrail.h>
 
 unsigned bus_freq_khz(void)
 {
@@ -47,13 +48,6 @@ unsigned long tsc_freq_mhz(void)
 	return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
 }
 
-#if !defined(__SMM__)
-#if !defined(__PRE_RAM__)
-#include <soc/ramstage.h>
-#else
-#include <soc/romstage.h>
-#endif
-
 void set_max_freq(void)
 {
 	msr_t perf_ctl;
@@ -76,5 +70,3 @@ void set_max_freq(void)
 
 	wrmsr(IA32_PERF_CTL, perf_ctl);
 }
-
-#endif /* __SMM__ */