diff options
| author | Derek Huang <derek.huang@intel.corp-partner.google.com> | 2021-03-15 12:11:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-19 11:22:07 +0000 |
| commit | 8056187e4eccd3fc56390498deb692cc16eacc9e (patch) | |
| tree | a5ceb6545f45db3f97587475e6fbae4ae132fcc9 /src/soc/intel | |
| parent | 9e82bf36c82159330f75a5fba6bb4c5ef37940fd (diff) | |
soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable
PmcUsb2PhySusPgEnable is enabled by default. Expose devicetree
parameter to disable
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ibd54a10c57d39bb8762b705ef0d6ff4cd47f0d89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index cbd687c67f..af9b310ba3 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -174,6 +174,8 @@ struct soc_intel_tigerlake_config { uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* PCH USB2 PHY Power Gating disable */ + uint8_t usb2_phy_sus_pg_disable; /* * Acoustic Noise Mitigation diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 0b2c0b0487..6d08e1f68c 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -443,6 +443,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Disable C1 C-state Demotion */ params->C1StateAutoDemotion = 0; + /* USB2 Phy Sus power gating setting override */ + params->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; + mainboard_silicon_init_params(params); } |