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authorJeremy Compostella <jeremy.compostella@intel.com>2022-08-03 09:59:16 -0700
committerMartin L Roth <gaumless@gmail.com>2022-08-07 19:46:52 +0000
commit7f96c05280904a1ad65ccc087035f26fb41efe8f (patch)
tree9b65d21bb9da9e9469a031846ae1d198083453a7 /src/soc/intel
parentb2af2e35f40e55cb07d6fb696e428fbe68ba2d3d (diff)
soc/intel/alderlake: Fix RPL-P 282 15W GT ICC MAX
The software used to read the document listing the VR settings turns out to not be perfectly compatible. Indeed, it displays a value of 55A for RPL-P 282 15W GT ICC MAX while the correct value actually is 40A. After a thorough review using the software used to create the document, it is the only value presenting a discrepancy. BRANCH=firmware-brya-14505.B BUG=b:239797178 TEST=build and boot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Iee293c87a66f0cd32714766e3ad81eee1a411723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/vr_config.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index 6112e6a27d..1a6c6bd4ff 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -86,7 +86,7 @@
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 41 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
- * | | GT | 3.2 | 3.2 | 55 | 41 | 28000 |
+ * | | GT | 3.2 | 3.2 | 40 | 41 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
*/
@@ -164,7 +164,7 @@ static const struct vr_lookup vr_config_icc[] = {
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
- { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 55) },
+ { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) },