diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-03-23 01:33:27 +0530 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-03-28 12:25:17 +0000 |
| commit | 7cb6d721161602f0cac2b340d1aa331c5aa262ae (patch) | |
| tree | 71c6d2b984acb65b9c2769d813bc4e54f8ed78b3 /src/soc/intel | |
| parent | 3ecc77722c9f7e857b9c034d4e01ee5f298b6c1f (diff) | |
soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:225544587
TEST=Able to build and boot brya. Also, verified the FSP debug log is
exactly same before and with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I665def977faaae45f6f834d75e8456859093ba49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4a27cb5f6e..bd2c0bea0e 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <fsp/api.h> +#include <fsp/fsp_debug_event.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <option.h> @@ -509,6 +510,8 @@ static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) + s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); /* PCH UART selection for FSP Debug */ s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2a02c21d22..2e76cd78c7 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -6,6 +6,7 @@ #include <cpu/intel/cpu_ids.h> #include <device/device.h> #include <drivers/wifi/generic/wifi.h> +#include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> @@ -364,6 +365,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_alderlake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) + arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); config = config_of_soc(); |