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authorSean Rhodes <sean@starlabs.systems>2024-01-10 20:38:05 +0000
committerFelix Held <felix-coreboot@felixheld.de>2024-02-05 14:09:05 +0000
commit7201602a18b63fc5236f025d22dc726637866cb6 (patch)
tree8372888b3a67a576d7a82e7f7ea3f1601817d37f /src/soc/intel
parent4f43b0e7adb7f4699bae7b9a2f2fac2e797e9c4c (diff)
soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
Currently, SOC_INTEL_COMMON_BLOCK_TCSS will set MUX to disabled. The two related options to re-configure it for either USB devices or displays, are currently only supported by the ChromeEC. As such, any device without the ChromeEC will boot with attached USB-C devices in a non-functional state. Add TCSS_HAS_USBC_OPS to make this feature configurable, and set the default to enabled if the board features the ChromeEC. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79882 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/tcss/Kconfig17
-rw-r--r--src/soc/intel/common/block/tcss/tcss.c19
2 files changed, 23 insertions, 13 deletions
diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig
index 4af75fc559..7a8f52cc54 100644
--- a/src/soc/intel/common/block/tcss/Kconfig
+++ b/src/soc/intel/common/block/tcss/Kconfig
@@ -2,17 +2,28 @@ config SOC_INTEL_COMMON_BLOCK_TCSS
def_bool n
select FSPS_USE_MULTI_PHASE_INIT
help
- Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state
+ Sets up USB2/3 port mapping in TCSS MUX
+
+config TCSS_HAS_USBC_OPS
+ bool "Enable USB-C MUX operations via the EC"
+ default y if EC_GOOGLE_CHROMEEC
+ depends on SOC_INTEL_COMMON_BLOCK_TCSS
+ help
+ Enable USB-C operations via the EC. Requires `usbc_get_ops` to control features
+ such as HPD and DP Mode entry. Currently, only the ChromeEC implements this, see
+ (ec/google/chromeec/usbc_mux.c).
+
+ This results in the MUX being set to a disabled state.
config ENABLE_TCSS_DISPLAY_DETECTION
bool "Enable detection of displays over USB Type-C ports with TCSS"
- depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP
+ depends on TCSS_HAS_USBC_OPS && RUN_FSP_GOP
help
Enable displays to be detected over Type-C ports during boot.
config ENABLE_TCSS_USB_DETECTION
bool "Enable detection of USB boot devices attached to USB Type-C ports with TCSS"
- depends on SOC_INTEL_COMMON_BLOCK_TCSS
+ depends on TCSS_HAS_USBC_OPS
help
Enable USB-C attached storage devices to be detected at boot.
This option is required for some payloads (eg, edk2), without which devices attached
diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c
index 7c58e3ae58..974aeb625a 100644
--- a/src/soc/intel/common/block/tcss/tcss.c
+++ b/src/soc/intel/common/block/tcss/tcss.c
@@ -442,23 +442,22 @@ void tcss_configure(const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PO
size_t i;
port_map = tcss_get_port_info(&num_ports);
- if (port_map == NULL)
+ if ((port_map == NULL) || platform_is_resuming())
return;
- if (!platform_is_resuming()) {
+ if (CONFIG(TCSS_HAS_USBC_OPS))
for (i = 0; i < num_ports; i++)
tcss_init_mux(i, &port_map[i]);
- /* This should be performed before alternate modes are entered */
- if (tcss_ops.configure_aux_bias_pads)
- tcss_ops.configure_aux_bias_pads(aux_bias_pads);
+ /* This should be performed before alternate modes are entered */
+ if (tcss_ops.configure_aux_bias_pads)
+ tcss_ops.configure_aux_bias_pads(aux_bias_pads);
- if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION))
- tcss_configure_dp_mode(port_map, num_ports);
+ if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION))
+ tcss_configure_dp_mode(port_map, num_ports);
- if (CONFIG(ENABLE_TCSS_USB_DETECTION))
- tcss_configure_usb_mode(port_map, num_ports);
- }
+ if (CONFIG(ENABLE_TCSS_USB_DETECTION))
+ tcss_configure_usb_mode(port_map, num_ports);
}
bool tcss_valid_tbt_auth(void)