diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-12-05 02:40:26 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-09 21:52:13 +0000 |
| commit | 715b787fd3d1a0e714da795ea3d3eaf28ca49577 (patch) | |
| tree | 36bddb19913ef007da7ba6d4aa29758e21ca189f /src/soc/intel | |
| parent | 2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8 (diff) | |
soc/intel/tigerlake: Hook up SMBus device to devicetree
Hook up `SmbusEnable` FSP setting to devicetree state and drop its
redundant devicetree setting `SmbusEnable`.
The following mainboards enable the SMBus device in the devicetree
despite `SmbusEnable` is not being set.
* google/deltaur
* starlabs/laptop
Thus, set it to off to keep the current state unchanged.
Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 2 |
2 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f0858db1b8..e729e8c0ee 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -272,9 +272,6 @@ struct soc_intel_tigerlake_config { /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* Gfx related */ uint8_t SkipExtGfxScan; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 40683e2a2e..24b8575357 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -130,7 +130,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ m_cfg->ChHashMask = 0x30CC; /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; |