soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake

Clone entirely from Jasperlake

List of changes on top off initial jasperlake clone
1. Rename from jasperlake to elkhartlake
2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op)

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

12 files changed, 1048 insertions, 0 deletions

diff --git a/src/soc/intel/elkhartlake/acpi/gpio.asl b/src/soc/intel/elkhartlake/acpi/gpio.asl
new file mode 100644
index 0000000000..ac0d1df5cb
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/gpio.asl
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/intel/common/acpi/gpio.asl>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+Device (GPIO)
+{
+	Name (_HID, CROS_GPIO_NAME)
+	Name (_UID, 0)
+	Name (_DDN, "GPIO Controller")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM1)
+		Memory32Fixed (ReadWrite, 0, 0, COM2)
+		Memory32Fixed (ReadWrite, 0, 0, COM4)
+		Memory32Fixed (ReadWrite, 0, 0, COM5)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+			{ GPIO_IRQ14 }
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		/* GPIO Community 0 */
+		CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+		CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+		BAS0 = ^^PCRB (PID_GPIOCOM0)
+		LEN0 = GPIO_BASE_SIZE
+
+		/* GPIO Community 1 */
+		CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+		CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+		BAS1 = ^^PCRB (PID_GPIOCOM1)
+		LEN1 = GPIO_BASE_SIZE
+
+		/* GPIO Community 2 */
+		CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
+		CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
+		BAS2 = ^^PCRB (PID_GPIOCOM2)
+		LEN2 = GPIO_BASE_SIZE
+
+		/* GPIO Community 4 */
+		CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+		CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+		BAS4 = ^^PCRB (PID_GPIOCOM4)
+		LEN4 = GPIO_BASE_SIZE
+
+		/* GPIO Community 5 */
+		CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+		CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
+		BAS5 = ^^PCRB (PID_GPIOCOM5)
+		LEN5 = GPIO_BASE_SIZE
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0xF)
+	}
+}
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+	/* GPIO Community 0 */
+	If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
+	{
+		Local0 = PID_GPIOCOM0
+		Local1 = Arg0 - GPIO_COM0_START
+	}
+	/* GPIO Community 1 */
+	If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
+	{
+		Local0 = PID_GPIOCOM1
+		Local1 = Arg0 - GPIO_COM1_START
+	}
+	/* GPIO Community 2 */
+	If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END)
+	{
+		Local0 = PID_GPIOCOM2
+		Local1 = Arg0 - GPIO_COM2_START
+	}
+	/* GPIO Community 4 */
+	If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
+	{
+		Local0 = PID_GPIOCOM4
+		Local1 = Arg0 - GPIO_COM4_START
+	}
+	/* GPIO Community 05*/
+	If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
+	{
+		Local0 = PID_GPIOCOM5
+		Local1 = Arg0 - GPIO_COM5_START
+	}
+
+	Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
+	Return (Local2)
+}
+
+/*
+ * Return PCR Port ID of GPIO Communities
+ *
+ * Arg0: GPIO Community (0-5)
+ */
+Method (GPID, 1, Serialized)
+{
+	Switch (ToInteger (Arg0))
+	{
+		Case (COMM_0) {
+			Local0 = PID_GPIOCOM0
+		}
+		Case (COMM_1) {
+			Local0 = PID_GPIOCOM1
+		}
+		Case (COMM_2) {
+			Local0 = PID_GPIOCOM2
+		}
+		Case (COMM_4) {
+			Local0 = PID_GPIOCOM4
+		}
+		Case (COMM_5) {
+			Local0 = PID_GPIOCOM5
+		}
+		Default {
+			Return (0)
+		}
+	}
+
+	Return (Local0)
+}
diff --git a/src/soc/intel/elkhartlake/acpi/pch_glan.asl b/src/soc/intel/elkhartlake/acpi/pch_glan.asl
new file mode 100644
index 0000000000..97faf7ac80
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/pch_glan.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel Gigabit Ethernet Controller 0:1f.6 */
+
+Device (GLAN)
+{
+	Name (_ADR, 0x001f0006)
+
+	Name (_S0W, 3)
+
+	Name (_PRW, Package() {GPE0_PME_B0, 4})
+
+	Method (_DSW, 3) {}
+}
diff --git a/src/soc/intel/elkhartlake/acpi/pch_hda.asl b/src/soc/intel/elkhartlake/acpi/pch_hda.asl
new file mode 100644
index 0000000000..340c76528d
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/pch_hda.asl
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Audio Controller - Device 31, Function 3 */
+
+Device (HDAS)
+{
+	Name (_ADR, 0x001f0003)
+	Name (_DDN, "Audio Controller")
+	Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+	/* Device is D3 wake capable */
+	Name (_S0W, 3)
+
+	/* NHLT Table Address populated from GNVS values */
+	Name (NBUF, ResourceTemplate () {
+		QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+			     MaxFixed, NonCacheable, ReadOnly,
+			     0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+	})
+
+	/*
+	 * Device Specific Method
+	 * Arg0 - UUID
+	 * Arg1 - Revision
+	 * Arg2 - Function Index
+	 */
+	Method (_DSM, 4)
+	{
+		If (Arg0 == ^UUID) {
+			/*
+			 * Function 0: Function Support Query
+			 * Returns a bitmask of functions supported.
+			 */
+			If (Arg2 == Zero) {
+				/*
+				 * NHLT Query only supported for revision 1 and
+				 * if NHLT address and length are set in NVS.
+				 */
+				If ((Arg1 == One) && ((NHLA != Zero) && (NHLL != Zero))) {
+					Return (Buffer (One) { 0x03 })
+				} Else {
+					Return (Buffer (One) { 0x01 })
+				}
+			}
+
+			/*
+			 * Function 1: Query NHLT memory address used by
+			 * Intel Offload Engine Driver to discover any non-HDA
+			 * devices that are supported by the DSP.
+			 *
+			 * Returns a pointer to NHLT table in memory.
+			 */
+			If (Arg2 == One) {
+				CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+				CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+				CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+
+				NBAS = NHLA
+				NMAS = NHLA
+				NLEN = NHLL
+
+				Return (NBUF)
+			}
+		}
+
+		Return (Buffer (One) { 0x00 })
+	}
+}
diff --git a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl
new file mode 100644
index 0000000000..aa494a76f9
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+	Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 },
+	Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 },
+	Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 },
+	Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 },
+
+	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+
+	Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 },
+	Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 },
+	Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 },
+	Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 },
+
+	Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 },
+
+	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+
+	Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 },
+
+	Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 },
+	Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 },
+	Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 },
+	Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 },
+
+	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+
+	Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 },
+	Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 },
+	Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 },
+	Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 },
+
+	Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ },
+	/* SA GNA Device */
+	Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 },
+	/* SA IPU Device */
+	Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 },
+	/* SA Thermal Device */
+	Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 },
+	/* SA IGFX Device */
+	Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 },
+})
+
+Name (PICN, Package () {
+	Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 },
+	Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 },
+	Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 },
+	Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 },
+
+	Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 },
+	Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 },
+	Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 },
+	Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 },
+
+	Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 },
+	Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 },
+	Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 },
+	Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 },
+
+	Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 },
+
+	Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 },
+	Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 },
+	Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 },
+
+	Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 },
+
+	Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 },
+	Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 },
+	Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 },
+	Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 },
+
+	Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 },
+	Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 },
+	Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 },
+	Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 },
+
+	Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 },
+	Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 },
+	Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 },
+	Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 },
+
+	Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 },
+	/* SA GNA Device */
+	Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 },
+	/* SA IPU Device */
+	Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, 0, PCH_IRQ11 },
+})
+
+Method (_PRT)
+{
+	If (PICM) {
+		Return (^PICP)
+	} Else {
+		Return (^PICN)
+	}
+}
diff --git a/src/soc/intel/elkhartlake/acpi/pcie.asl b/src/soc/intel/elkhartlake/acpi/pcie.asl
new file mode 100644
index 0000000000..a19feb7168
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/pcie.asl
@@ -0,0 +1,301 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel PCH PCIe support */
+
+Method (IRQM, 1, Serialized) {
+
+	/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
+	Name (IQAA, Package () {
+		Package () { 0x0000ffff, 0, 0, 16 },
+		Package () { 0x0000ffff, 1, 0, 17 },
+		Package () { 0x0000ffff, 2, 0, 18 },
+		Package () { 0x0000ffff, 3, 0, 19 } })
+	Name (IQAP, Package () {
+		Package () { 0x0000ffff, 0, 0, 11 },
+		Package () { 0x0000ffff, 1, 0, 10 },
+		Package () { 0x0000ffff, 2, 0, 11 },
+		Package () { 0x0000ffff, 3, 0, 11 } })
+
+	/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
+	Name (IQBA, Package () {
+		Package () { 0x0000ffff, 0, 0, 17 },
+		Package () { 0x0000ffff, 1, 0, 18 },
+		Package () { 0x0000ffff, 2, 0, 19 },
+		Package () { 0x0000ffff, 3, 0, 16 } })
+	Name (IQBP, Package () {
+		Package () { 0x0000ffff, 0, 0, 10 },
+		Package () { 0x0000ffff, 1, 0, 11 },
+		Package () { 0x0000ffff, 2, 0, 11 },
+		Package () { 0x0000ffff, 3, 0, 11 } })
+
+	/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
+	Name (IQCA, Package () {
+		Package () { 0x0000ffff, 0, 0, 18 },
+		Package () { 0x0000ffff, 1, 0, 19 },
+		Package () { 0x0000ffff, 2, 0, 16 },
+		Package () { 0x0000ffff, 3, 0, 17 } })
+	Name (IQCP, Package () {
+		Package () { 0x0000ffff, 0, 0, 11 },
+		Package () { 0x0000ffff, 1, 0, 11 },
+		Package () { 0x0000ffff, 2, 0, 11 },
+		Package () { 0x0000ffff, 3, 0, 10 } })
+
+	/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
+	Name (IQDA, Package () {
+		Package () { 0x0000ffff, 0, 0, 19 },
+		Package () { 0x0000ffff, 1, 0, 16 },
+		Package () { 0x0000ffff, 2, 0, 17 },
+		Package () { 0x0000ffff, 3, 0, 18 } })
+	Name (IQDP, Package () {
+		Package () { 0x0000ffff, 0, 0, 11 },
+		Package () { 0x0000ffff, 1, 0, 11 },
+		Package () { 0x0000ffff, 2, 0, 10 },
+		Package () { 0x0000ffff, 3, 0, 11 } })
+
+	Switch (ToInteger (Arg0))
+	{
+		Case (Package () { 1, 5, 9, 13 }) {
+			If (PICM) {
+				Return (IQAA)
+			} Else {
+				Return (IQAP)
+			}
+		}
+
+		Case (Package () { 2, 6, 10, 14 }) {
+			If (PICM) {
+				Return (IQBA)
+			} Else {
+				Return (IQBP)
+			}
+		}
+
+		Case (Package () { 3, 7, 11, 15 }) {
+			If (PICM) {
+				Return (IQCA)
+			} Else {
+				Return (IQCP)
+			}
+		}
+
+		Case (Package () { 4, 8, 12, 16 }) {
+			If (PICM) {
+				Return (IQDA)
+			} Else {
+				Return (IQDP)
+			}
+		}
+
+		Default {
+			If (PICM) {
+				Return (IQDA)
+			} Else {
+				Return (IQDP)
+			}
+		}
+	}
+}
+
+Device (RP01)
+{
+	Name (_ADR, 0x001C0000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001C0001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001C0002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001C0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP05)
+{
+	Name (_ADR, 0x001C0004)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP06)
+{
+	Name (_ADR, 0x001C0005)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP07)
+{
+	Name (_ADR, 0x001C0006)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP08)
+{
+	Name (_ADR, 0x001C0007)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP09)
+{
+	Name (_ADR, 0x001D0000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP10)
+{
+	Name (_ADR, 0x001D0001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP11)
+{
+	Name (_ADR, 0x001D0002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP12)
+{
+	Name (_ADR, 0x001D0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
diff --git a/src/soc/intel/elkhartlake/acpi/platform.asl b/src/soc/intel/elkhartlake/acpi/platform.asl
new file mode 100644
index 0000000000..4b01aeb464
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/platform.asl
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+/* Generic indicator for sleep state */
+#include <soc/intel/common/acpi/platform.asl>
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	PICM = Arg0
+}
diff --git a/src/soc/intel/elkhartlake/acpi/pmc.asl b/src/soc/intel/elkhartlake/acpi/pmc.asl
new file mode 100644
index 0000000000..ea4134b0fa
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/pmc.asl
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/iomap.h>
+
+Scope (\_SB.PCI0) {
+
+	Device (PMC)
+	{
+		Name (_HID, "INTC1026")
+		Name (_DDN, "Intel(R) Elkhart Lake IPC Controller")
+		/*
+		 * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
+		 * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
+		 */
+		Name (_CRS, ResourceTemplate () {
+			Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000)
+		})
+	}
+}
diff --git a/src/soc/intel/elkhartlake/acpi/scs.asl b/src/soc/intel/elkhartlake/acpi/scs.asl
new file mode 100644
index 0000000000..b58608feed
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/scs.asl
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pcr_ids.h>
+
+Scope (\_SB.PCI0) {
+
+	/*
+	 * Clear register 0x1C20/0x4820
+	 * Arg0 - PCR Port ID
+	 */
+	Method(SCSC, 1, Serialized)
+	{
+		PCRA (Arg0, 0x1C20, 0x0)
+		PCRA (Arg0, 0x4820, 0x0)
+	}
+
+	/* EMMC */
+	Device(PEMC) {
+		Name(_ADR, 0x001A0000)
+		Name (_DDN, "eMMC Controller")
+		Name (TEMP, 0)
+
+		OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
+		Field(SCSR, WordAcc, NoLock, Preserve) {
+			Offset (0x84),	/* PMECTRLSTATUS */
+			PMCR, 16,
+			Offset (0xA2),	/* PG_CONFIG */
+			, 2,
+			PGEN, 1,	/* PG_ENABLE */
+		}
+
+		Method(_INI) {
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_EMMC)
+		}
+
+		Method(_PS0, 0, Serialized) {
+			Stall (50) // Sleep 50 us
+
+			PGEN = 0 // Disable PG
+
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_EMMC)
+
+			/* Set Power State to D0 */
+			PMCR = PMCR & 0xFFFC
+			TEMP = PMCR
+		}
+
+		Method(_PS3, 0, Serialized) {
+			PGEN = 1 // Enable PG
+
+			/* Set Power State to D3 */
+			PMCR = PMCR | 0x0003
+			TEMP = PMCR
+		}
+
+		Device (CARD)
+		{
+			Name (_ADR, 0x00000008)
+			Method (_RMV, 0, NotSerialized)
+			{
+				Return (0)
+			}
+		}
+	}
+
+	/* SD CARD */
+	Device (SDXC)
+	{
+		Name (_ADR, 0x00140005)
+		Name (_DDN, "SD Controller")
+		Name (TEMP, 0)
+		Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))
+
+		OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
+		Field (SDPC, WordAcc, NoLock, Preserve)
+		{
+			Offset (0x84),	/* PMECTRLSTATUS */
+			PMCR, 16,
+			Offset (0xA2),	/* PG_CONFIG */
+			, 2,
+			PGEN, 1,	/* PG_ENABLE */
+		}
+
+		/*
+		 * _DSM x86 Device Specific Method
+		 * Arg0: UUID Unique function identifier
+		 * Arg1: Integer Revision Level
+		 * Arg2: Integer Function Index (0 = Return Supported Functions)
+		 * Arg3: Package Parameters
+		 */
+		Method (_DSM, 4)
+		{
+			If (Arg0 == DSUU) {
+				/* Check the revision */
+				If (Arg1 >= 0) {
+					/*
+					 * Function Index 0 the return value is a buffer containing
+					 * one bit for each function index, starting with zero.
+					 * Bit 0 - Indicates whether there is support for any
+					 *         functions other than function 0.
+					 * Bit 1 - Indicates support to clear power control register
+					 * Bit 2 - Indicates support to set power control register
+					 * Bit 3 - Indicates support to set 1.8V signalling
+					 * Bit 4 - Indicates support to set 3.3V signalling
+					 * Bit 5 - Indicates support for HS200 mode
+					 * Bit 6 - Indicates support for HS400 mode
+					 * Bit 9 - Indicates eMMC I/O Driver Strength
+					 */
+					/*
+					 * For SD we have to support functions to
+					 * set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
+					 */
+					If (Arg2 == 0) {
+						Return (Buffer () { 0x19 })
+					}
+					/*
+					 * Function Index 3: Set 1.8v signalling.
+					 * We put a sleep of 100ms in this method to
+					 * work around a known issue with detecting
+					 * UHS SD card on PCH. This is to compensate
+					 * for the SD VR slowness.
+					 */
+					If (Arg2 == 3) {
+						Sleep (100)
+						Return(Buffer () { 0x00 })
+					}
+					/*
+					 * Function Index 4: Set 3.3v signalling.
+					 * We put a sleep of 100ms in this method to
+					 * work around a known issue with detecting
+					 * UHS SD card on PCH. This is to compensate
+					 * for the SD VR slowness.
+					 */
+					If (Arg2 == 4) {
+						Sleep (100)
+						Return(Buffer () { 0x00 })
+					}
+				}
+			}
+			Return(Buffer() { 0x0 })
+		}
+
+		Method(_INI)
+		{
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_SDX)
+		}
+
+		Method (_PS0, 0, Serialized)
+		{
+			PGEN = 0 /* Disable PG */
+
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_SDX)
+
+			/* Set Power State to D0 */
+			PMCR = PMCR & 0xFFFC
+			TEMP = PMCR
+
+			/* Change pad mode to Native */
+			GPMO(SD_PWR_EN_PIN, 0x1)
+		}
+
+		Method (_PS3, 0, Serialized)
+		{
+			PGEN = 1 /* Enable PG */
+
+			/* Set Power State to D3 */
+			PMCR = PMCR | 0x0003
+			TEMP = PMCR
+
+			/* Change pad mode to GPIO control */
+			GPMO(SD_PWR_EN_PIN, 0x0)
+
+			/* Enable Tx Buffer */
+			GTXE(SD_PWR_EN_PIN, 0x1)
+
+			/* Drive TX to zero */
+			CTXS(SD_PWR_EN_PIN)
+		}
+
+		Device (CARD)
+		{
+			Name (_ADR, 0x00000008)
+			Method (_RMV, 0, NotSerialized)
+			{
+				Return (1)
+			}
+		}
+	} /* Device (SDXC) */
+}
diff --git a/src/soc/intel/elkhartlake/acpi/serialio.asl b/src/soc/intel/elkhartlake/acpi/serialio.asl
new file mode 100644
index 0000000000..f7bf452058
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/serialio.asl
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel Serial IO Devices */
+
+Device (I2C0)
+{
+	Name (_ADR, 0x00150000)
+	Name (_DDN, "Serial IO I2C Controller 0")
+}
+
+Device (I2C1)
+{
+	Name (_ADR, 0x00150001)
+	Name (_DDN, "Serial IO I2C Controller 1")
+}
+
+Device (I2C2)
+{
+	Name (_ADR, 0x00150002)
+	Name (_DDN, "Serial IO I2C Controller 2")
+}
+
+Device (I2C3)
+{
+	Name (_ADR, 0x00150003)
+	Name (_DDN, "Serial IO I2C Controller 3")
+}
+
+Device (I2C4)
+{
+	Name (_ADR, 0x00190000)
+	Name (_DDN, "Serial IO I2C Controller 4")
+}
+
+Device (I2C5)
+{
+	Name (_ADR, 0x00190001)
+	Name (_DDN, "Serial IO I2C Controller 5")
+}
+
+Device (SPI0)
+{
+	Name (_ADR, 0x001e0002)
+	Name (_DDN, "Serial IO SPI Controller 0")
+}
+
+Device (SPI1)
+{
+	Name (_ADR, 0x001e0003)
+	Name (_DDN, "Serial IO SPI Controller 1")
+}
+
+Device (SPI2)
+{
+	Name (_ADR, 0x00120006)
+	Name (_DDN, "Serial IO SPI Controller 2")
+}
+
+Device (SPI3)
+{
+	Name (_ADR, 0x00130000)
+	Name (_DDN, "Serial IO SPI Controller 3")
+}
+
+Device (UAR0)
+{
+	Name (_ADR, 0x001e0000)
+	Name (_DDN, "Serial IO UART Controller 0")
+}
+
+Device (UAR1)
+{
+	Name (_ADR, 0x001e0001)
+	Name (_DDN, "Serial IO UART Controller 1")
+}
+
+Device (UAR2)
+{
+	Name (_ADR, 0x00190002)
+	Name (_DDN, "Serial IO UART Controller 2")
+}
diff --git a/src/soc/intel/elkhartlake/acpi/smbus.asl b/src/soc/intel/elkhartlake/acpi/smbus.asl
new file mode 100644
index 0000000000..6705f22693
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/smbus.asl
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel SMBus Controller 0:1f.4 */
+
+Device (SBUS)
+{
+	Name (_ADR, 0x001f0004)
+}
diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl
new file mode 100644
index 0000000000..fd874697f5
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pcr_ids.h>
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
+/* PCR access */
+#include <soc/intel/common/acpi/pcr.asl>
+
+/* GPIO controller */
+#include "gpio.asl"
+
+/* ESPI 0:1f.0 */
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
+
+/* PCH HDA */
+#include "pch_hda.asl"
+
+/* PCIE Ports */
+#include "pcie.asl"
+
+/* pmc 0:1f.2 */
+#include "pmc.asl"
+
+/* Serial IO */
+#include "serialio.asl"
+
+/* SMBus 0:1f.4 */
+#include "smbus.asl"
+
+/* USB XHCI 0:14.0 */
+#include "xhci.asl"
+
+/* PCI _OSC */
+#include <soc/intel/common/acpi/pci_osc.asl>
+
+/* PMC Core*/
+#include <soc/intel/common/block/acpi/acpi/pmc.asl>
+
+/* EMMC/SD card */
+#include "scs.asl"
diff --git a/src/soc/intel/elkhartlake/acpi/xhci.asl b/src/soc/intel/elkhartlake/acpi/xhci.asl
new file mode 100644
index 0000000000..445c7dbcea
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/xhci.asl
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name (_ADR, 0x00140000)
+
+	Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+	Name (_S3D, 3)	/* D3 supported in S3 */
+	Name (_S0W, 3)	/* D3 can wake device in S0 */
+	Name (_S3W, 3)	/* D3 can wake system from S3 */
+
+	Method (_PS0, 0, Serialized)
+	{
+
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+
+	}
+
+	/* Root Hub for Elkhartlake PCH */
+	Device (RHUB)
+	{
+		Name (_ADR, Zero)
+
+		/* USB2 */
+		Device (HS01) { Name (_ADR, 1) }
+		Device (HS02) { Name (_ADR, 2) }
+		Device (HS03) { Name (_ADR, 3) }
+		Device (HS04) { Name (_ADR, 4) }
+		Device (HS05) { Name (_ADR, 5) }
+		Device (HS06) { Name (_ADR, 6) }
+		Device (HS07) { Name (_ADR, 7) }
+		Device (HS08) { Name (_ADR, 8) }
+
+		/* USB3 */
+		Device (SS01) { Name (_ADR, 9) }
+		Device (SS02) { Name (_ADR, 10) }
+		Device (SS03) { Name (_ADR, 11) }
+		Device (SS04) { Name (_ADR, 12) }
+		Device (SS05) { Name (_ADR, 13) }
+		Device (SS06) { Name (_ADR, 14) }
+	}
+}