diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-31 15:15:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-01 08:22:28 +0000 |
| commit | 6e82ebff73d0a2a9d29248885b30384f1f550376 (patch) | |
| tree | f19901e9a5228dd1cb2c8f9a40e0328feba331a0 /src/soc/intel | |
| parent | 6724ba4f045cbbe2326463cbeaf59becfb01342e (diff) | |
mb/ocp/deltalake: Fill ECC type in romstage
Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.
Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/romstage.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 6025f2a6d0..c1cb0caeea 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -37,6 +37,25 @@ static const struct SystemMemoryMapHob *get_system_memory_map(void) return *memmap_addr; } +static uint8_t get_error_correction_type(const uint8_t RasModesEnabled) +{ + switch (RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + /* Save the DIMM information for SMBIOS table 17 */ void save_dimm_info(void) { @@ -63,6 +82,7 @@ void save_dimm_info(void) /* According to Dear Customer Letter it's 1.12 TB per processor. */ mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET; mem_info->number_of_devices = CONFIG_DIMM_MAX; + mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled); dimm_max = ARRAY_SIZE(mem_info->dimm); vdd_voltage = get_ddr_voltage(hob->DdrVoltage); /* For now only implement for one socket and hard-coded for DDR4 */ |