diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-04-24 17:37:13 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-07-13 01:05:06 +0000 |
| commit | 6a6550be4f80296210893c05d83b0545e8567c2d (patch) | |
| tree | a7cf7ba8734727b99ee60fdbce520c2d2fc6bf69 /src/soc/intel | |
| parent | 4ee03dc445cf4f4b625d85141c442e03e6a64d00 (diff) | |
soc/intel/alderlake: Disable SaGV reordering
Disable re-ordering SaGv point on warm reset so that most
performant SaGv point is picked after memory training and
boot time is reduced.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index e41cd842c8..5d717b8e54 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -93,6 +93,9 @@ chip soc/intel/alderlake # Reduce the size of BasicMemoryTests to speed up the boot time. register "lower_basic_mem_test_size" = "true" + # Disable SaGV reordering operation to start with SaGV point 4 and reduce boot time. + register "disable_sagv_reorder" = "true" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |