diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-25 15:39:55 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-29 15:13:47 +0000 |
| commit | 670572ff6a4d0822df91c34114b7afdb21efd85c (patch) | |
| tree | 4d4ec176274e466806452bfa14e7522dd90b0176 /src/soc/intel | |
| parent | 4b1f4e3a993fe42bdc83966fba0d657a12d023d4 (diff) | |
soc/intel/cmn/cse: Enforce CSE disabling
This patch enforces disabling of the CSE device if CSE stays in
SOFT TEMP DISABLE state. The recommendation is to make CSE function
disable to avoid receiving any CSE commands from the OS layer.
BUG=b:228789015
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 64fd0412e2..d284a9d638 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1203,7 +1203,8 @@ static void cse_set_state(struct device *dev) * 1. Send EOP to CSE if not done. * 2. Perform global reset lock. * 3. Put HECI1 to D0i3 and disable the HECI1 if the user selects - * DISABLE_HECI1_AT_PRE_BOOT config. + * DISABLE_HECI1_AT_PRE_BOOT config or CSE HFSTS1 Operation Mode is + * `Software Temporary Disable`. */ static void cse_final_ready_to_boot(void) { @@ -1212,7 +1213,7 @@ static void cse_final_ready_to_boot(void) cse_control_global_reset_lock(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) { + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) { cse_set_to_d0i3(); heci1_disable(); } |