diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2024-11-11 17:34:12 -0700 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2024-11-14 16:33:44 +0000 |
| commit | 618fbe0d210d50275492521a7c31a04202ef9a7e (patch) | |
| tree | 4da0f2cf6d54aa42d524ca0e7487bc4dc7969e16 /src/soc/intel | |
| parent | 3d32f915a9c4d60046574690db966d1f14eebe65 (diff) | |
soc/intel/alderlake: Display early Sign of Life for CSE FW Sync
This will ensure that the user is informed about an ongoing CSE FW Sync.
BUG=b:378458829
TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed
during CSE FW Sync.
Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/ux.h | 5 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index d2abaee532..d3a2884018 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -205,8 +205,13 @@ void mainboard_romstage_entry(void) } } - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { + cse_fill_bp_info(); + if (CONFIG(CHROMEOS_ENABLE_ESOL) && + is_cse_fw_update_required() && !is_cse_boot_to_rw()) + ux_inform_user_of_update_operation("CSE update"); cse_fw_sync(); + } /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); diff --git a/src/soc/intel/alderlake/romstage/ux.h b/src/soc/intel/alderlake/romstage/ux.h index e7e1d9957e..14c10e7ffd 100644 --- a/src/soc/intel/alderlake/romstage/ux.h +++ b/src/soc/intel/alderlake/romstage/ux.h @@ -1,3 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ +#define _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ + bool ux_inform_user_of_update_operation(const char *name); + +#endif /* _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ */ |