diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-11 13:04:02 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-19 21:02:59 +0000 |
| commit | 5611cfd55f6ad558a000a02e84e65af42316edd5 (patch) | |
| tree | c16f6eb5b55e6ccc3f6423afa4dcfddad45afae1 /src/soc/intel | |
| parent | 2ffd2198863fe8e971b56fc146339cc4dbd56295 (diff) | |
soc/intel/cnl: lock AES-NI feature if selected
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of
AES-NI enablement as precaution, as suggested in Intel document
325384-070US.
Locking is enabled by default (as already done in SKL and Arrandale) and
may be disabled by the newly introduced Kconfig in the parent change.
Tested by checking the MSR.
Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 3d97c56404..ddedb3fed2 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -199,6 +199,8 @@ void soc_core_init(struct device *cpu) /* Configure Intel Speed Shift */ configure_isst(); + set_aesni_lock(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); |