diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2023-10-27 15:18:22 -0500 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-11-03 15:33:50 +0000 |
| commit | 4f961371a5d48335e64623ee0840840b34fd25c3 (patch) | |
| tree | ad6e55e50fc046d279423cc4af147ea30ddfdd7f /src/soc/intel | |
| parent | 96a7d9e76bb8fc008fb907c6234f0aee294d32f7 (diff) | |
soc/intel/braswell: Unify DPTF enablement
Currently, there are 3 separate settings for DPTF which are not always
in sync:
- the enabled/disabled state of the devicetree PCI device
- the 'dptf_enable' register, which sets the ACPI device status via GNVS
- the 'DptfDisable' register, which sets the FSP UPD of the same name
To make things sane, drop the two chip registers, and set the GNVS
variable and FSP UPD based on the enabled/disabled status of the DPTF
PCI device in the mainboard's devicetree.
TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI
devices are present/enabled when DPTF is enabled in devicetree, and not
present/disabled when disabled in devicetree.
Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/braswell/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/braswell/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 3 |
3 files changed, 2 insertions, 7 deletions
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index a278e55742..718bfe995d 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -70,9 +70,7 @@ size_t size_of_dnvs(void) void soc_fill_gnvs(struct global_nvs *gnvs) { - const struct soc_intel_braswell_config *config = config_of_soc(); - - gnvs->dpte = config->dptf_enable; + gnvs->dpte = is_devfn_enabled(PCI_DEVFN(PUNIT_DEV, 0)); /* Fill in the Wi-Fi Region ID */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index ce394d0baa..d3c41f8894 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -79,7 +79,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->AzaliaConfigPtr = 0; params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; params->ChvSvidConfig = config->ChvSvidConfig; - params->DptfDisable = config->DptfDisable; + params->DptfDisable = !is_devfn_enabled(PCI_DEVFN(PUNIT_DEV, 0)); params->PcdEmmcMode = config->PcdEmmcMode; params->PcdUsb3ClkSsc = 1; params->PcdDispClkSsc = 1; diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 53627be577..de86a12488 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -42,8 +42,6 @@ enum usb_comp_bg_value { struct soc_intel_braswell_config { bool enable_xdp_tap; - bool dptf_enable; - enum serirq_mode serirq_mode; /* Disable SLP_X stretching after SUS power well loss */ @@ -104,7 +102,6 @@ struct soc_intel_braswell_config { uint8_t PcdEnableI2C6; uint8_t PunitPwrConfigDisable; uint8_t ChvSvidConfig; - uint8_t DptfDisable; uint8_t PcdEmmcMode; uint8_t Usb2Port0PerPortPeTxiSet; uint8_t Usb2Port0PerPortTxiSet; |