diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-04-24 17:13:58 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-07-13 01:04:49 +0000 |
| commit | 4ee03dc445cf4f4b625d85141c442e03e6a64d00 (patch) | |
| tree | 107c4629d21fae8fc9fa03d342074e046f09e4ec /src/soc/intel | |
| parent | 433343eaaa987432242909fe4b1b482d53b66b4a (diff) | |
soc/intel/alderlake: Reduce memory test size
Enable upd to reduce size of the memory test.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index ed8ae049fa..e41cd842c8 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -90,6 +90,9 @@ chip soc/intel/alderlake .tdp_pl4 = 114, }" + # Reduce the size of BasicMemoryTests to speed up the boot time. + register "lower_basic_mem_test_size" = "true" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |