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| author | Alicja Michalska <ahplka19@gmail.com> | 2024-03-01 01:39:15 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-03-05 23:29:17 +0000 |
| commit | 4d9549b95fe15d3cdd2cf975dfffd4760602e23b (patch) | |
| tree | b3f7b166e71fe50f3c67c7fbc9da5154172e6642 /src/soc/intel | |
| parent | 5015a35f48aebb22e18b526be737b4ece5759a69 (diff) | |
soc/intel: Add definition of D0 stepping for TigerLake Halo
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/report_platform.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index bd435454d9..3cff6215d4 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -71,6 +71,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_TIGERLAKE_P0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_R0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 1ecaf77ab5..8f90b3c6a3 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -25,6 +25,7 @@ static struct { } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, { CPUID_TIGERLAKE_B0, "Tigerlake B0" }, + { CPUID_TIGERLAKE_P0, "Tigerlake P0" }, { CPUID_TIGERLAKE_R0, "Tigerlake R0" }, }; |