diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2024-06-06 12:14:39 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-06-07 06:16:19 +0000 |
| commit | 491afc3cc778ba82154f405061922da5024357c5 (patch) | |
| tree | ca685f7e97094334f829c9a3547f73d6456b33e5 /src/soc/intel | |
| parent | bfb39806c9edbfee7383c99a73e228a5314ee2c2 (diff) | |
soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs
PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N
FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating
programming for ADL_N FSP.
Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index ff5c83c3af..d7b30c64da 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -932,7 +932,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) +#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 |