diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-11-11 18:36:27 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-12 04:58:31 +0000 |
| commit | 3f3ea8bb58f8fc65148047b9d2f3274589a6636a (patch) | |
| tree | 24a7e883d38f8ef82f7f7168fec42cf97923958e /src/soc/intel | |
| parent | 11ff6e22b3d39a9a26973ccdcd5dd6c2431dbfd9 (diff) | |
soc/intel/pantherlake: Add config option to limit DRAM frequency
This patch adds a new config option to limit the maximum DRAM
frequency for Pantherlake platforms.
The mainboard code should try to set `max_dram_speed_mts` from
override device tree if required.
BUG=b:373394046
TEST=Able to build and boot google/fatcat.
Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/pantherlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/romstage/fsp_params.c | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index b59ce5e8e6..5846037c95 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -512,6 +512,8 @@ struct soc_intel_pantherlake_config { */ uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + uint16_t max_dram_speed_mts; + }; typedef struct soc_intel_pantherlake_config config_t; diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index b105d3d58a..e6ed19ec85 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -74,6 +74,9 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; } + if (config->max_dram_speed_mts) + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + m_cfg->RMT = config->rmt; m_cfg->MrcFastBoot = 1; } |