diff options
| author | John Zhao <john.zhao@intel.com> | 2020-10-16 10:09:35 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-19 07:00:05 +0000 |
| commit | 33f234e3561c8cc5b9426fdf88067f2c9ced1052 (patch) | |
| tree | d859d9ae8cd5a257dc5a32804260a09b05bc5b8b /src/soc/intel | |
| parent | b37d4b95d3821a4f83067f8db0c652456f33f10c (diff) | |
soc/intel/cannonlake: Fix memory corruptions
Coverity detects source memory is overrun. Fix this issue by using
the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption.
Found-by: Coverity CID 1429762 1429774
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d66e890a9e..fe7641f27b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -355,14 +355,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + sizeof(config->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented, sizeof(config->PcieRpSlotImplemented)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + sizeof(config->PcieRpHotPlug)); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; |