summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorAndrey Petrov <anpetrov@fb.com>2020-03-22 22:27:44 -0700
committerAndrey Petrov <anpetrov@fb.com>2020-03-26 02:53:26 +0000
commit335384d2b75eb0266c6f13b52e20b2d3bba390ea (patch)
treedc9e6dab2178508915c66e948be2363d0aa36826 /src/soc/intel
parent403f215cb4e2486d0b89ec97978263948fbc7ce6 (diff)
soc/intel/xeon_sp: Configure P2SB BAR in bootblock
In order to use early serial output we need to enable P2SB BAR0, because that allows PCR access to PCH registers. TEST=tested on OCP Tioga Pass Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/xeon_sp/bootblock.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 453c383897..8e236f2942 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <intelblocks/lpc_lib.h>
+#include <soc/pci_devs.h>
const FSPT_UPD temp_ram_init_params = {
.FspUpdHeader = {
@@ -54,6 +55,11 @@ void bootblock_soc_early_init(void)
{
fast_spi_early_init(SPI_BASE_ADDRESS);
pch_enable_lpc();
+
+ /* Set up P2SB BAR. This is needed for PCR to work */
+ uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
+ pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
+ pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
}
void bootblock_soc_init(void)