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authorMaximilian Brune <maximilian.brune@9elements.com>2023-01-04 19:22:35 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-05-05 12:36:29 +0000
commit27900ea9f85f81a55246f1c27d662f92121c0563 (patch)
treec1d93c0b29a0833bd87c50fdc15ce6c57087c9fa /src/soc/intel
parent03bf97ad163bc5bcc98c6ed0af096f80a7a32127 (diff)
src/soc/intel: Document meaning of variables
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/chip.h4
-rw-r--r--src/soc/intel/common/block/include/intelblocks/meminit.h4
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pcie_rp.h1
-rw-r--r--src/soc/intel/meteorlake/chip.h4
4 files changed, 7 insertions, 6 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index c4662123d0..699d163aa0 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -154,8 +154,8 @@ enum ddi_ports {
};
enum ddi_port_flags {
- DDI_ENABLE_DDC = 1 << 0,
- DDI_ENABLE_HPD = 1 << 1,
+ DDI_ENABLE_DDC = 1 << 0, // Display Data Channel
+ DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
};
/*
diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h
index 3ebf5368a1..a4fb9fa1f3 100644
--- a/src/soc/intel/common/block/include/intelblocks/meminit.h
+++ b/src/soc/intel/common/block/include/intelblocks/meminit.h
@@ -22,8 +22,8 @@
/* Different memory topologies supported by the platform. */
enum mem_topology {
- MEM_TOPO_MEMORY_DOWN = BIT(0),
- MEM_TOPO_DIMM_MODULE = BIT(1),
+ MEM_TOPO_MEMORY_DOWN = BIT(0), // memory is soldered onto board
+ MEM_TOPO_DIMM_MODULE = BIT(1), // memory is composed of DIMM modules
MEM_TOPO_MIXED = MEM_TOPO_MEMORY_DOWN | MEM_TOPO_DIMM_MODULE,
};
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index a4e350055e..be7c5f93f8 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -15,6 +15,7 @@
enum pcie_rp_flags {
PCIE_RP_HOTPLUG = (1 << 0),
+ /* PCIE RP Latency Tolerance Report */
PCIE_RP_LTR = (1 << 1),
/* PCIE RP Advanced Error Report */
PCIE_RP_AER = (1 << 2),
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index d87a67c3c6..f63d977d9e 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -51,8 +51,8 @@ enum ddi_ports {
};
enum ddi_port_flags {
- DDI_ENABLE_DDC = 1 << 0,
- DDI_ENABLE_HPD = 1 << 1,
+ DDI_ENABLE_DDC = 1 << 0, // Display Data Channel
+ DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
};
/*