diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-04-17 16:13:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-19 07:52:43 +0000 |
| commit | 26be35a50720f7dc60aa6a28dae151b47cb782ce (patch) | |
| tree | f114b460a7c9346c183a726d7fa969765e8e997c /src/soc/intel | |
| parent | afabaede2c20d22fc00d40eddf3d0dd01a591932 (diff) | |
soc/intel/cannonlake: Set DISB after Dram init
DRAM Initialization Scratchpad Bit needs to be set after Dram
Initialization finished, according to Cannonlake PCH-LP EDS(#565870)
chapter 5.3.1.
BUG=None
Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/pmutil.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a5d18330df..951d8863ac 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -128,6 +128,21 @@ const char *const *soc_std_gpe_sts_array(size_t *a) return gpe_sts_bits; } +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + uint8_t disb_val; + /* Only care about bits [23:16] of register GEN_PMCON_A */ + uint8_t *addr = (void *)(pmc_mmio_regs() + GEN_PMCON_A + 2); + + disb_val = read8(addr); + disb_val |= (DISB >> 16); + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); + write8(addr, disb_val); +} + /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index dc9652689a..c8cb927078 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -123,6 +123,7 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + pmc_set_disb(); if (!s3wake) save_dimm_info(); if (postcar_frame_init(&pcf, 1 * KiB)) |