diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-06-02 19:07:56 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-05 00:30:19 +0200 |
| commit | 22b2c793e3587fb98d42f88e5e623621e055ff3a (patch) | |
| tree | 91681692dd6c622ab6737b735eb689599954fba4 /src/soc/intel | |
| parent | 1041d399cbbae9042a021502f9e105b078f5046e (diff) | |
soc/intel/apollolake: Add config for cpu base clock frequency
Add config for cpu base clock frequency(Mhz), use and
clean up code.
Change-Id: I724c48c11796aa942295d4f19cc629d4c13647e1
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/20017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/tsc_freq.c | 2 |
3 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 56f0d203b2..fe72c078f7 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -322,4 +322,8 @@ config IFD_CHIPSET string default "aplk" +config CPU_BCLK_MHZ + int + default 100 + endif diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 3391597396..0900eef640 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -32,8 +32,6 @@ void enable_untrusted_mode(void); #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 -#define BASE_CLOCK_MHZ 100 - /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000 diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c index f91a047d08..885311c555 100644 --- a/src/soc/intel/apollolake/tsc_freq.c +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -26,7 +26,7 @@ unsigned long tsc_freq_mhz(void) { msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); + return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff)); } void set_max_freq(void) |