diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-08-15 15:40:59 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-21 15:02:31 +0000 |
| commit | 1e71fe107a001d8947dabd733ce0076fd80bc56f (patch) | |
| tree | f7278183ab01384322e5a9276c26c6020d982d97 /src/soc/intel | |
| parent | 28f1729f157924f37e0a875898404d36fb7a9954 (diff) | |
soc/intel: Enable TME based on supported CPU SKU and config option
This patch removes the static kconfig being used to fill in TME enable
FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check
if the CPU has required TME support rather than hardcoding.
TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the
TME-supported CPU SKUs.
As per FSP-M debug log:
Without this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ] TmeEnable = 0x1
With this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ] TmeEnable = 0x0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 3 |
3 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 71a1a5c92c..c0bdb0de2b 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -177,7 +177,7 @@ static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, { /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - m_cfg->TmeEnable = CONFIG(INTEL_TME); + m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); } static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 82927f7ca3..bd88c158de 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -134,7 +134,7 @@ static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, { /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - m_cfg->TmeEnable = CONFIG(INTEL_TME); + m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); } static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index a9cb2ece4e..399cb87fe1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -206,8 +206,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuPcieRpEnableMask |= 1 << i; } - /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ - m_cfg->TmeEnable = CONFIG(INTEL_TME); + m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); /* crashLog config */ m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); |