diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-12-13 01:08:06 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-15 13:22:53 +0000 |
| commit | 0b7388f0504b9ac849857681ee14c5ff4b2cc73c (patch) | |
| tree | 23018b6289f5380d4ec24762dea399e64e826fe9 /src/soc/intel | |
| parent | 053c901548b751dd10eeae5e0afae8359290bede (diff) | |
soc/intel/cmn/cpu: Introduce API to disable signaling 3-strike event
This patch introduces a new API to disable signaling the 3-strike event
on Intel Meteor Lake C0 (QS) stepping and subsequent SoCs. This is
necessary because the existing event handling mechanism is incompatible
with the new hardware design.
Disabling the 3-strike event registration prevents the 3-strike count
from increasing, which addresses bug b:314883362. This issue can potentially lead to system instability.
BUG=b:314883362
TEST=disabling the 3-strike event on a Google Screebo system with QS silicon.
Change-Id: I15bd5a93da34d7f2a127c21c4cd8b5952926bccf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79472
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 2 |
3 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index bf361a4791..1cefc1277e 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -505,3 +505,12 @@ void disable_three_strike_error(void) msr.lo = msr.lo | DISABLE_CPU_ERROR; wrmsr(MSR_PREFETCH_CTL, msr); } + +void disable_signaling_three_strike_event(void) +{ + msr_t msr; + + msr = rdmsr(MSR_DISABLE_SIGNALING_THREE_STRIKE_EVENT); + msr.lo = msr.lo | THREE_STRIKE_COUNT; + wrmsr(MSR_DISABLE_SIGNALING_THREE_STRIKE_EVENT, msr); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 5601d5d067..91c76e393c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -217,4 +217,12 @@ bool is_keylocker_supported(void); */ void disable_three_strike_error(void); +/* + * This function stops the Three Strike event from signaling and prevent + * the Three Strike Counter from incrementing. + * This is the new MSR introduces starting from Intel Meteor Lake-C0 (QS) stepping SoC + * It helps to collect more useful CPU traces for debugging. + */ +void disable_signaling_three_strike_event(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 9f95e9f7e6..158cc9e3fe 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -41,6 +41,8 @@ #define MISC_PWR_MGMT_ISST_EN (1 << 6) #define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) #define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) +#define MSR_DISABLE_SIGNALING_THREE_STRIKE_EVENT 0x1ab +#define THREE_STRIKE_COUNT (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_PRMRR_PHYS_BASE 0x1f4 #define MSR_PRMRR_PHYS_MASK 0x1f5 |