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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-09-13 08:28:05 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-15 17:02:20 +0000 |
| commit | 08a4d4de3ba4589e745a212772b1399af31c91ed (patch) | |
| tree | e59e5107ea0a21b21f6556c362c5fe47abc7e243 /src/soc/intel | |
| parent | e3d9b0aa3f511cea5f2adcc7a27dfac2baf61e67 (diff) | |
xeon_sp/spr: Fix duplicated defines
Change-Id: Ib365a17652b8531e865fa16eae837c68cbedbca8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h | 45 |
1 files changed, 1 insertions, 44 deletions
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 8d112cb7fc..06ec16c0ec 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -5,18 +5,16 @@ #include <device/pci_def.h> #include <device/pci_type.h> +#include <soc/pch_pci_devs.h> #include <types.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0) -#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func) #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) -#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0) -#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) #endif #define UNCORE_BUS_0 0 @@ -155,47 +153,6 @@ #define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) #endif -/* PCH Device info */ - -#define XHCI_BUS_NUMBER 0x0 -#define PCH_DEV_SLOT_XHCI 0x14 -#define XHCI_FUNC_NUM 0x0 -#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) -#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) -#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) - - -#define PCH_DEV_SLOT_CSE 0x16 -#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) -#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) -#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) -#define PCH_DEV_CSE _PCH_DEV(CSE, 0) -#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) -#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) - -#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) - -#define HPET_BUS_NUM 0x0 -#define HPET_DEV_NUM PCH_DEV_SLOT_LPC -#define HPET0_FUNC_NUM 0x00 - -#define PCH_IOAPIC_BUS_NUMBER 0xF0 -#define PCH_IOAPIC_DEV_NUM 0x1F -#define PCH_IOAPIC_FUNC_NUM 0x00 - -// ========== IOAPIC Definitions for DMAR/ACPI ======== -#define PCH_IOAPIC_ID 0x08 - /* Root port Registers */ /* IEH */ |