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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-12-13 12:31:46 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-26 10:51:22 +0000
commit086f0faf756a2d4e71fd9c1d27335af240418b19 (patch)
treed80d93faf567f9cebfbdfe11742c9acd7afb3f58 /src/soc/intel
parenta8ab2b33a41ac05899885608c6ca9fcd658859b6 (diff)
soc/intel/cannonlake: Move GPIO PM configuration to soc level
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/acpi/gpio.asl41
-rw-r--r--src/soc/intel/cannonlake/acpi/lpit.asl17
-rw-r--r--src/soc/intel/common/acpi/platform.asl15
3 files changed, 73 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl
index 65332ad7c0..7702ad556c 100644
--- a/src/soc/intel/cannonlake/acpi/gpio.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio.asl
@@ -157,3 +157,44 @@ Method (CGPM, 2, Serialized)
PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_ENABLE_GPIO_PM_CONFIG))
}
}
+
+/* GPIO Power Management bits */
+Name(GPMB, Package(TOTAL_GPIO_COMM) {0})
+
+/*
+ * Save GPIO Power Management bits
+ */
+Method (SGPM, 0, Serialized)
+{
+ For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+ {
+ Local1 = GPID (Local0)
+ GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG)
+ }
+}
+
+/*
+ * Restore GPIO Power Management bits
+ */
+Method (RGPM, 0, Serialized)
+{
+ For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+ {
+ CGPM (Local0, DerefOf(GPMB[Local0]))
+ }
+}
+
+/*
+ * Save current setting of GPIO Power Management bits and
+ * enable all Power Management bits for all communities
+ */
+Method (EGPM, 0, Serialized)
+{
+ /* Save current setting and will restore it when resuming */
+ SGPM ()
+ /* Enable PM bits */
+ For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+ {
+ CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ }
+}
diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl
index 74d4fe6396..e0e23cac4e 100644
--- a/src/soc/intel/cannonlake/acpi/lpit.asl
+++ b/src/soc/intel/cannonlake/acpi/lpit.asl
@@ -16,6 +16,8 @@
External(\_SB.MS0X, MethodObj)
External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj)
+External(\_SB.PCI0.EGPM, MethodObj)
+External(\_SB.PCI0.RGPM, MethodObj)
scope(\_SB)
{
@@ -73,6 +75,15 @@ scope(\_SB)
If (CondRefOf (\_SB.MS0X)) {
\_SB.MS0X(1)
}
+
+ /*
+ * Save the current PM bits then
+ * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
+ */
+ If (CondRefOf (\_SB.PCI0.EGPM))
+ {
+ \_SB.PCI0.EGPM ()
+ }
}
/*
* Function 6 - Low Power S0 Exit Notification
@@ -87,6 +98,12 @@ scope(\_SB)
If (CondRefOf (\_SB.MS0X)) {
\_SB.MS0X(0)
}
+
+ /* Restore GPIO all Community PM */
+ If (CondRefOf (\_SB.PCI0.RGPM))
+ {
+ \_SB.PCI0.RGPM ()
+ }
}
}
Return(Buffer(One) {0x00})
diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl
index 9aa2edc6df..c41ccbe0cb 100644
--- a/src/soc/intel/common/acpi/platform.asl
+++ b/src/soc/intel/common/acpi/platform.asl
@@ -19,6 +19,8 @@
External(\_SB.MPTS, MethodObj)
External(\_SB.MWAK, MethodObj)
+External(\_SB.PCI0.EGPM, MethodObj)
+External(\_SB.PCI0.RGPM, MethodObj)
/* Port 80 POST */
@@ -41,6 +43,14 @@ Method (_PTS, 1)
{
\_SB.MPTS (Arg0)
}
+ /*
+ * Save the current PM bits then
+ * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
+ */
+ If (CondRefOf (\_SB.PCI0.EGPM))
+ {
+ \_SB.PCI0.EGPM ()
+ }
}
/* The _WAK method is called on system wakeup */
@@ -53,6 +63,11 @@ Method (_WAK, 1)
{
\_SB.MWAK (Arg0)
}
+ /* Restore GPIO all Community PM */
+ If (CondRefOf (\_SB.PCI0.RGPM))
+ {
+ \_SB.PCI0.RGPM ()
+ }
Return (Package(){0,0})
}