Consolidate reset API, add generic reset_prepare mechanism

There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.

This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).

Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.

Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

8 files changed, 15 insertions, 38 deletions

diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 56273cc03e..15e78fe203 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -23,13 +23,13 @@
 
 #define CSE_WAIT_MAX_MS							1000
 
-void global_reset(void)
+void do_global_reset(void)
 {
 	global_reset_enable(1);
-	hard_reset();
+	do_hard_reset();
 }
 
-void reset_prepare(void)
+void soc_reset_prepare(enum reset_type reset_type)
 {
 	struct stopwatch sw;
 
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
index fd38f61255..e38a2e6ec8 100644
--- a/src/soc/intel/baytrail/reset.c
+++ b/src/soc/intel/baytrail/reset.c
@@ -29,13 +29,13 @@ void warm_reset(void)
 	outb(RST_CPU | SYS_RST, RST_CNT);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	/* Sends INIT# to CPU */
 	outb(RST_CPU, RST_CNT);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Don't power cycle on hard_reset(). It's not really clear what the
 	 * semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
index e4d01c2790..ad90dcd880 100644
--- a/src/soc/intel/broadwell/reset.c
+++ b/src/soc/intel/broadwell/reset.c
@@ -28,12 +28,12 @@
  * with ETR[20] set.
  */
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x06, 0xcf9);
 }
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index e9be1855b0..06a534ce99 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -25,39 +25,16 @@
 #define RST_CPU			(1 << 2)
 #define SYS_RST			(1 << 1)
 
-#ifdef __ROMCC__
-#define WEAK
-#else
-#define WEAK __attribute__((weak))
-#endif
-
-void WEAK reset_prepare(void) { /* do nothing */ }
-
 #if IS_ENABLED(CONFIG_HAVE_HARD_RESET)
-void hard_reset(void)
+void do_hard_reset(void)
 {
-	reset_prepare();
 	/* S0->S5->S0 trip. */
 	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
-	while (1)
-		hlt();
 }
 #endif
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
-	reset_prepare();
 	/* PMC_PLTRST# asserted. */
 	outb(RST_CPU | SYS_RST, RST_CNT);
-	while (1)
-		hlt();
-}
-
-void cpu_reset(void)
-{
-	reset_prepare();
-	/* Sends INIT# to CPU */
-	outb(RST_CPU, RST_CNT);
-	while (1)
-		hlt();
 }
diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c
index fd38f61255..e38a2e6ec8 100644
--- a/src/soc/intel/fsp_baytrail/reset.c
+++ b/src/soc/intel/fsp_baytrail/reset.c
@@ -29,13 +29,13 @@ void warm_reset(void)
 	outb(RST_CPU | SYS_RST, RST_CNT);
 }
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	/* Sends INIT# to CPU */
 	outb(RST_CPU, RST_CNT);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	/* Don't power cycle on hard_reset(). It's not really clear what the
 	 * semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c
index 7e1c582749..78d74939e3 100644
--- a/src/soc/intel/fsp_broadwell_de/reset.c
+++ b/src/soc/intel/fsp_broadwell_de/reset.c
@@ -23,7 +23,7 @@ void warm_reset(void)
     outb(0x06, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	warm_reset();
 }
diff --git a/src/soc/intel/sch/reset.c b/src/soc/intel/sch/reset.c
index 2574565f75..91bcd690ca 100644
--- a/src/soc/intel/sch/reset.c
+++ b/src/soc/intel/sch/reset.c
@@ -17,12 +17,12 @@
 #include <arch/io.h>
 #include <reset.h>
 
-void soft_reset(void)
+void do_soft_reset(void)
 {
 	outb(0x04, 0xcf9);
 }
 
-void hard_reset(void)
+void do_hard_reset(void)
 {
 	outb(0x02, 0xcf9);
 	outb(0x06, 0xcf9);
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 69109145f2..dee98a4c1e 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -41,7 +41,7 @@ static void do_force_global_reset(void)
 	hard_reset();
 }
 
-void global_reset(void)
+void do_global_reset(void)
 {
 	if (send_global_reset() != 0) {
 		/* If ME unable to reset platform then