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authorLijian Zhao <lijian.zhao@intel.com>2019-01-15 17:37:50 -0800
committerDuncan Laurie <dlaurie@chromium.org>2019-01-16 21:45:40 +0000
commitc3e75b42a471cc64fec37a464eef7088492ec04e (patch)
treec2d248aa53d85e6db5110056e94b8bf42a98a0da /src/soc/intel
parent314094fea6e91a99f1d971c406d871a8b925fbce (diff)
soc/intel/cannonlake: Fix afterg3 programming
According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC memory mapped register but not pci config spaces. Change the programming to affect that difference. BUG=b:122425492 TEST=Change System Power State after failure to "s5 off", and boot up onto sarien platform, check the register with iotools mmio_read32 0xfe001020 and bit 0 is set. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e Reviewed-on: https://review.coreboot.org/c/30945 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/pmc.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index aebcfc9482..4dabb2ecef 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -33,8 +33,9 @@
static void pmc_set_afterg3(struct device *dev, int s5pwr)
{
uint8_t reg8;
+ uint8_t *pmcbase = pmc_mmio_regs();
- reg8 = pci_read_config8(dev, GEN_PMCON_B);
+ reg8 = read8(pmcbase + GEN_PMCON_A);
switch (s5pwr) {
case MAINBOARD_POWER_STATE_OFF:
@@ -48,7 +49,7 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr)
break;
}
- pci_write_config8(dev, GEN_PMCON_B, reg8);
+ write8(pmcbase + GEN_PMCON_A, reg8);
}
/*