soc/intel/skylake: Fix broken suspend-resume

With recent change (a4b11e5c90: soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) to perform CPU MP init before FSP-S init, suspend
resume is currently broken for all skylake/kabylake boards. All the
skylake/kabylake boards store external stage cache in TSEG, which is
relocated post MP-init. Thus, if FSP loading and initialization is
done after MP-init, then ramstage is not able to:
1. Save FSP component in external stage cache during normal boot, and
2. Load FSP component from external stage cache during resume

In order to fix this, ensure that FSP loading happens separately from
FSP initialization. Add fsp_load callback for pre_mp_init which ensures
that the required FSP component is loaded/saved from/to external stage
cache.

BUG=chrome-os-partner:63114
BRANCH=None
TEST=Verified that 100 cycles of suspend/resume worked fine on poppy.

Change-Id: I5b4deaf936a05b9bccf2f30b949674e2ba993488
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18414
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 13 insertions, 1 deletions

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 060c4ee0a5..744f5491a1 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -33,6 +33,11 @@ void soc_init_pre_device(void *chip_info)
 	intel_silicon_init();
 }
 
+void soc_fsp_load(void)
+{
+	fsp_load();
+}
+
 static void pci_domain_set_resources(device_t dev)
 {
 	assign_resources(dev->link_list);
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 97a37e8afc..2b50d0c85b 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -40,6 +40,11 @@ void soc_init_pre_device(void *chip_info)
 	fsp_silicon_init(romstage_handoff_is_resume());
 }
 
+void soc_fsp_load(void)
+{
+	fsps_load(romstage_handoff_is_resume());
+}
+
 static void pci_domain_set_resources(device_t dev)
 {
 	assign_resources(dev->link_list);
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index e9bb29f7a6..d1a684ca60 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -478,7 +478,7 @@ static const struct mp_ops mp_ops = {
 	 * that are set prior to ramstage.
 	 * Real MTRRs programming are being done after resource allocation.
 	 */
-	.pre_mp_init = NULL,
+	.pre_mp_init = soc_fsp_load,
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = smm_info,
 	.get_microcode_info = get_microcode_info,
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
index f1a9e535be..a0c8a17bb9 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -29,6 +29,7 @@
 void soc_irq_settings(FSP_SIL_UPD *params);
 void pch_enable_dev(device_t dev);
 void soc_init_pre_device(void *chip_info);
+void soc_fsp_load(void);
 const char *soc_acpi_name(struct device *dev);
 int init_igd_opregion(igd_opregion_t *igd_opregion);
 extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index 136c4f2647..79362fff17 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -28,6 +28,7 @@
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
 void pch_enable_dev(device_t dev);
+void soc_fsp_load(void);
 void soc_init_pre_device(void *chip_info);
 void soc_irq_settings(FSP_SIL_UPD *params);
 const char *soc_acpi_name(struct device *dev);