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authorSubrata Banik <subrata.banik@intel.com>2016-07-27 05:30:50 +0530
committerAndrey Petrov <andrey.petrov@intel.com>2016-07-28 05:29:46 +0200
commita90f41bdd71bd3f98c683702f90247e674a50896 (patch)
tree460f30c32ed03a6ea494a4f155fbdea7359c937a /src/soc/intel
parent89f6d6079ef88ff20c7da3422d1298d614ed6b5a (diff)
intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init
FSP temp ram init was getting called earlier from ROMCC bootblock. Now with C entry boot block, it is needed to locate FSP header and call FspTempRamInit. Hence add fsp 1_1 driver code to locate FSP Temp ram and execute. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built kunimitsu and ensure FSP Temp Ram Init return success Change-Id: If40b267777a8dc5c473d1115b19b98609ff3fd74 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15787 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/bootblock/bootblock.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 028bb7b314..ab1720c83a 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <bootblock_common.h>
+#include <fsp/bootblock.h>
#include <soc/bootblock.h>
#include <soc/romstage.h>
@@ -33,13 +34,15 @@ void bootblock_soc_early_init(void)
pch_uart_init();
}
-/*
- * Perform early chipset initialization before fsp memory init
- * example: pirq->irq programming, enabling smbus, pmcbase, abase,
- * get platform info, i2c programming
- */
void bootblock_soc_init(void)
{
+ /* locate and call FspTempRamInit */
+ bootblock_fsp_temp_ram_init();
+ /*
+ * Perform early chipset initialization before fsp memory init
+ * example: pirq->irq programming, enabling smbus, pmcbase, abase,
+ * get platform info, i2c programming
+ */
report_platform_info();
set_max_freq();
pch_early_init();