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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-01-18 20:00:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-25 08:54:51 +0000 |
| commit | 8331833c89b3413ed4c3aef4a4cab762620911d0 (patch) | |
| tree | 460a397725f73eb4da643138b651a4e596379d5d /src/soc/intel | |
| parent | a626d2ed6f15748f40500cef1ec074ed9fd785df (diff) | |
soc/intel/xeon_sp/cpx: Fix loading MCU on APs
Commit 393992f (cpu/mp_init: Fix microcode lock) fixed the semantics
of parallel loading microcode updates.
So now '*parallel = 1' really means loading MCU in parallel, which
seems to fail inconsistently on around 10% of the APs.
Change-Id: I755dd302abbb58537d840852e8e290bea282a674
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49671
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/cpu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 2f4ab0663e..4dea1a40a6 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -51,10 +51,15 @@ static void xeon_configure_mca(void) mca_configure(); } +/* + * On server platforms the FIT mechanism only updates the microcode on + * the BSP. Loading MCU on AP in parallel seems to fail in 10% of the cases + * so do it serialized. + */ void get_microcode_info(const void **microcode, int *parallel) { *microcode = intel_mp_current_microcode(); - *parallel = 1; + *parallel = 0; } const void *intel_mp_current_microcode(void) |