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authorAaron Durbin <adurbin@chromium.org>2016-08-11 23:51:42 -0500
committerMartin Roth <martinroth@google.com>2016-08-19 18:15:24 +0200
commit7b2c781dbdb226af1db10547500be91f45ee8cc0 (patch)
treeeb664b275a3a704428b035c9d6a36f06b4de3d76 /src/soc/intel
parent6f1155916a8b2f5409d0992963a1c16178794a48 (diff)
soc/intel/apollolake: use SPI flash boot_device_rw() for ealy stages
If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: If5e3d06008d5529dd6d7c05d374a81ba172d58fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16201 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 0c7f27a88a..db4559c9d1 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
# CPU specific options
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
@@ -49,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI
- select SPI_FLASH
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER