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authorAngel Pons <th3fanbus@gmail.com>2020-12-11 16:48:47 +0100
committerHung-Te Lin <hungte@chromium.org>2020-12-14 08:18:52 +0000
commit70d8baef921c50a49e055de3ed32cca618820c11 (patch)
tree7710035fb1699a7cdc7aafcc2b322941aa69f73c /src/soc/intel
parent030db31aa8c5966f3a2b5596ff98b5116a47de47 (diff)
soc/intel/jasperlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/jasperlake/chip.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 2fc32c9840..9d4bc5c80a 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -129,22 +129,13 @@ struct soc_intel_jasperlake_config {
/* Enable if SD Card Power Enable Signal is Active High */
uint8_t SdCardPowerEnableActiveHigh;
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* VR Config Settings for IA Core */
uint16_t ImonSlope;
uint16_t ImonOffset;
/* Gfx related */
- uint8_t IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
-
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;