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authorKane Chen <kane.chen@intel.com>2014-09-09 15:53:09 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-02 17:27:26 +0200
commit642e598102a48a5ffd76aae0d21795881a56c6d8 (patch)
tree4846438cac7ccc3673d4310983d775867fc65778 /src/soc/intel
parent86b0c8b48038f537407c1b8ed9015a54d0159403 (diff)
broadwell: Update PCIe configuration to follow BWG
According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11 BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/broadwell/pcie.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index bd1c55a372..f63f6d527c 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -113,6 +113,7 @@ static void root_port_init_config(device_t dev)
rpc.pin_ownership = pci_read_config32(dev, 0x410);
root_port_config_update_gbe_port();
+ pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4));
if (dev->chip_info != NULL) {
config_t *config = dev->chip_info;
rpc.coalesce = config->pcie_port_coalesce;