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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-09-29 22:01:47 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-10-12 08:53:18 +0000
commit5acea15d63e821a1bc416d206162ed030cd5d57c (patch)
tree2cfb6df75bee65567a17127382a4c0a4c2d6ee0e /src/soc/intel
parent463e44bedbf3d5f24b8e6e19475b5155b523309a (diff)
soc/intel/jasperlake: Allow mainboard to override chip configuration
Add a weak override function to allow mainboard to override chip configuration like GPIO PM. BUG=None TEST=Build and boot waddledee to OS. Ensure that the suspend/resume sequence works fine. Change-Id: I40fa655b0324dc444182b988f0089587e3877a47 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c8
-rw-r--r--src/soc/intel/jasperlake/include/soc/ramstage.h1
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 1919936003..bf279ecf31 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -78,6 +78,11 @@ static void parse_devicetree(FSP_S_CONFIG *params)
sizeof(config->SerialIoUartMode));
}
+__weak void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config)
+{
+ /* Override settings per board. */
+}
+
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
@@ -86,6 +91,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
FSP_S_CONFIG *params = &supd->FspsConfig;
struct soc_intel_jasperlake_config *config = config_of_soc();
+ /* Allow mainboard to override any chip config */
+ mainboard_update_soc_chip_config(config);
+
/* Parse device tree and fill in FSP UPDs */
parse_devicetree(params);
diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h
index 8188fbdb84..1de8e37758 100644
--- a/src/soc/intel/jasperlake/include/soc/ramstage.h
+++ b/src/soc/intel/jasperlake/include/soc/ramstage.h
@@ -9,6 +9,7 @@
#include <soc/soc_chip.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config);
void soc_init_pre_device(void *chip_info);
#endif