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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-09 11:41:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:32:44 +0000
commit544878b56349a74e8cb7a0e9af899b5f7fc246fc (patch)
tree0a586dcbe6e70c94be6b7d123f43dd7c294dad68 /src/soc/intel
parent5bc641afebda5fd274ba713add4145651d9bc71d (diff)
arch/x86: Add postcar_frame_common_mtrrs()
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c8
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c6
2 files changed, 2 insertions, 12 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index acdf2613fa..8361bb1972 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -62,6 +62,8 @@ static void prepare_and_run_postcar(struct postcar_frame *pcf)
fill_postcar_frame(pcf);
+ postcar_frame_common_mtrrs(pcf);
+
run_postcar_phase(pcf);
/* We do not return here. */
}
@@ -256,12 +258,6 @@ static void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index ca478f7313..5ae39dd767 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -39,12 +39,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.