diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-08-11 06:52:07 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-14 20:59:33 +0000 |
| commit | 4e9687c4162257f52e1b19283e6f5bbe3244b9ed (patch) | |
| tree | feabe3961d3d04311fdf30dd866c06cf7030370f /src/soc/intel | |
| parent | e1528fe3588a63fa712fe7d0dee1c9d2a47e7a48 (diff) | |
soc/intel/skylake: Use PEG definitions from pci_devs.h
Change-Id: I7114deed35f25e74ac508f08e9c85653a7fe39ed
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 5d651cabd1..7410925a1f 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -170,7 +170,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, * If PEG port is not defined in the device tree, it will be disabled * in FSP */ - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ + dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ if (!dev || !dev->enabled) m_cfg->Peg0Enable = 0; else if (dev->enabled) { @@ -185,7 +185,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg0Gen3EqPh3Method = 0; } - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */ + dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ if (!dev || !dev->enabled) m_cfg->Peg1Enable = 0; else if (dev->enabled) { @@ -197,7 +197,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg1Gen3EqPh3Method = 0; } - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */ + dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ if (!dev || !dev->enabled) m_cfg->Peg2Enable = 0; else if (dev->enabled) { |