cbtable: remove chromeos_acpi from cbtable

Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.

BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725

Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

11 files changed, 6 insertions, 21 deletions

diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index c7be979553..3250aeb277 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -53,6 +53,6 @@ typedef struct global_nvs_t {
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;
 } __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
 #endif	/* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index b4fe65e7d9..bc6f7ec5de 100644
--- a/src/soc/intel/baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
 #include <stdint.h>
 #include <compiler.h>
 
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET	0x1000
-
 #define LPSS_NVS_SIO_DMA1	0
 #define LPSS_NVS_I2C1		1
 #define LPSS_NVS_I2C2		2
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 21cdb142a4..715929d7ea 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -102,7 +102,7 @@ typedef struct global_nvs_t {
 	/* Baytrail LPSS (0x1000) */
 	device_nvs_t dev;
 } __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
 #ifdef __SMM__
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 268655e7cb..8ed534eb91 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -20,9 +20,6 @@
 #include <stdint.h>
 #include <compiler.h>
 
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET	0x1000
-
 #define LPSS_NVS_SIO_DMA1	0
 #define LPSS_NVS_I2C1		1
 #define LPSS_NVS_I2C2		2
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 89a434bf8b..05831bb7d1 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -106,7 +106,7 @@ typedef struct global_nvs_t {
 	/* LPSS (0x1000) */
 	device_nvs_t dev;
 } __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
 #if ENV_SMM
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h
index 15240d13b4..d17b3d461e 100644
--- a/src/soc/intel/broadwell/include/soc/device_nvs.h
+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
 #include <stdint.h>
 #include <compiler.h>
 
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET	0x1000
-
 #define SIO_NVS_DMA		0
 #define SIO_NVS_I2C0		1
 #define SIO_NVS_I2C1		2
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 34673d55bc..2e51e1bd20 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -94,7 +94,7 @@ typedef struct global_nvs_t {
 	/* Device specific (0x1000) */
 	device_nvs_t dev;
 } __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
 #ifdef __SMM__
diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h
index 6c64f3ac2c..1e5562566d 100644
--- a/src/soc/intel/cannonlake/include/soc/nvs.h
+++ b/src/soc/intel/cannonlake/include/soc/nvs.h
@@ -46,7 +46,7 @@ typedef struct global_nvs_t {
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;
 }  __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
 
 #endif
diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
index 5bafea6fd0..8eff8cdb6f 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
 #include <stdint.h>
 #include <compiler.h>
 
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET	0x1000
-
 #define LPSS_NVS_SIO_DMA1	0
 #define LPSS_NVS_I2C1		1
 #define LPSS_NVS_I2C2		2
diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h
index 02c9e65809..2b7d1267fc 100644
--- a/src/soc/intel/skylake/include/soc/device_nvs.h
+++ b/src/soc/intel/skylake/include/soc/device_nvs.h
@@ -20,9 +20,6 @@
 #include <stdint.h>
 #include <compiler.h>
 
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET	0x1000
-
 #define SIO_NVS_I2C0		0
 #define SIO_NVS_I2C1		1
 #define SIO_NVS_I2C2		2
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index bd3610e654..53fdded8e9 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -102,6 +102,6 @@ typedef struct global_nvs_t {
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;
 } __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
 #endif