soc/intel/common/block: Add Intel common systemagent support

Create common Intel systemagent code.
This code currently contains the SA initialization
required in Bootblock phase, which has the following programming-
* Set PCIEXBAR
* Clear TSEG register
More code will get added up in the subsequent phases.

Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 123 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
new file mode 100644
index 0000000000..77248bbb1a
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_SA_H
+#define SOC_INTEL_COMMON_BLOCK_SA_H
+
+/* Device 0:0.0 PCI configuration space */
+
+#define MCHBAR          0x48
+#define PCIEXBAR        0x60
+#define  PCIEXBAR_LENGTH_64MB       2
+#define  PCIEXBAR_LENGTH_128MB      1
+#define  PCIEXBAR_LENGTH_256MB      0
+#define  PCIEXBAR_PCIEXBAREN        (1 << 0)
+#define GGC             0x50
+
+#define TOUUD           0xa8    /* Top of Upper Usable DRAM */
+#define BDSM            0xb0    /* Base Data Stolen Memory */
+#define BGSM            0xb4    /* Base GTT Stolen Memory */
+#define TSEG            0xb8    /* TSEG base */
+#define TOLUD           0xbc    /* Top of Low Used Memory */
+
+void bootblock_systemagent_early_init(void);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_SA_H */
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
new file mode 100644
index 0000000000..773a56b831
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -0,0 +1,26 @@
+config SOC_INTEL_COMMON_BLOCK_SA
+	bool
+	help
+	  Intel Processor common System Agent support
+
+config MMCONF_BASE_ADDRESS
+	hex "PCI MMIO Base Address"
+	default 0xe0000000
+
+config SA_PCIEX_LENGTH
+	hex
+	default 0x10000000 if (PCIEX_LENGTH_256MB)
+	default 0x8000000 if (PCIEX_LENGTH_128MB)
+	default 0x4000000 if (PCIEX_LENGTH_64MB)
+	default 0x10000000
+	help
+	  This option allows you to select length of PCIEX region.
+
+config PCIEX_LENGTH_256MB
+	bool "256MB"
+
+config PCIEX_LENGTH_128MB
+	bool "128MB"
+
+config PCIEX_LENGTH_64MB
+	bool "64MB"
diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc
new file mode 100644
index 0000000000..75d5626cea
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Makefile.inc
@@ -0,0 +1 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
new file mode 100644
index 0000000000..58e2c7e054
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <commonlib/helpers.h>
+#include <intelblocks/systemagent.h>
+#include <soc/pci_devs.h>
+
+void bootblock_systemagent_early_init(void)
+{
+	uint32_t reg;
+	uint8_t pciexbar_length;
+
+	/*
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+	reg = 0;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
+
+	/* Get PCI Express Region Length */
+	switch (CONFIG_SA_PCIEX_LENGTH) {
+	case 256 * MiB:
+		pciexbar_length = PCIEXBAR_LENGTH_256MB;
+		break;
+	case 128 * MiB:
+		pciexbar_length = PCIEXBAR_LENGTH_128MB;
+		break;
+	case 64 * MiB:
+		pciexbar_length = PCIEXBAR_LENGTH_64MB;
+		break;
+	default:
+		pciexbar_length = PCIEXBAR_LENGTH_256MB;
+	}
+	reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
+				| PCIEXBAR_PCIEXBAREN;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+
+	/*
+	 * TSEG defines the base of SMM range. BIOS determines the base
+	 * of TSEG memory which must be at or below Graphics base of GTT
+	 * Stolen memory, hence its better to clear TSEG register early
+	 * to avoid power on default non-zero value (if any).
+	 */
+	pci_write_config32(SA_DEV_ROOT, TSEG, 0);
+}
+