diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-27 16:39:31 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:17:48 +0000 |
| commit | fbd5367b1c8d5d95063fc03930effb8f54c96831 (patch) | |
| tree | 52aed6a98a133156fd4ae64d2c7150b61b57aac9 /src/soc/intel | |
| parent | fe85ae3f41912ce021c0ffe9a0cfcf4798da5da1 (diff) | |
skylake: iomap: Remove unused RCBA region
Remove the now unused RCBA base and size from iomap.h
and fix a trivial typo that doesn't seem to get used
anywhere.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emege-glados coreboot
Change-Id: If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee7b1a8a75a9e9dc191c16ddc32b6a38acec398c
Original-Change-Id: I0c49803d47105c3c55121caedaffaa249c4f0189
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295906
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11533
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 916719d893..333906b348 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -28,7 +28,7 @@ #define MCFG_BASE_SIZE 0x4000000 #define PCH_PCR_BASE_ADDRESS 0xfd000000 -#define PCH_BCR_BASE_SIZE 0x1000000 +#define PCH_PCR_BASE_SIZE 0x1000000 #define UART_DEBUG_BASE_ADDRESS 0xfe034000 #define UART_DEBUG_BASE_SIZE 0x1000 @@ -48,10 +48,6 @@ #define GDXC_BASE_ADDRESS 0xfed84000 #define GDXC_BASE_SIZE 0x1000 -/* TODO: need to remove RCBA code after ASL clean up */ -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x4000 - #define HPET_BASE_ADDRESS 0xfed00000 #define PCH_PWRM_BASE_ADDRESS 0xfe000000 |