diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-01-21 14:28:26 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-23 05:06:12 +0000 |
| commit | f8d9a13aba3b7a82934914bce3b820c428ff98f3 (patch) | |
| tree | 3c1d3650a6d2e9d9a8f4e9b8c6eec2598e4fb839 /src/soc/intel | |
| parent | 6476e415124731c9082d92263f4e99645a6f1424 (diff) | |
soc/intel/common: Update SA bit fields as per EDS
This patch updates system agent related registers bit definitions
as per EDS.
For example:
As per CNL/ICL EDS MCHBAR register base is between bit 16-38
but coreboot programming was not aligned with EDS previously.
CNL EDS doc number: 566216
Also provide provision to program 64bit values as per SA EDS definitions
TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.
Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/systemagent.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent_early.c | 15 |
2 files changed, 11 insertions, 8 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index c60595835a..a11bf647d2 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -43,13 +43,13 @@ void bootblock_systemagent_early_init(void); * Fixed MMIO range * INDEX = Either PCI configuration space registers or MMIO offsets * mapped from REG. - * BASE = 32 bit Address. + * BASE = 64 bit Address. * SIZE = base length * DESCRIPTION = Name of the register/offset. */ struct sa_mmio_descriptor { unsigned int index; - uintptr_t base; + uint64_t base; size_t size; const char *description; }; diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index d6f129d679..1273c0f30f 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -71,7 +71,7 @@ void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, int i; for (i = 0; i < count; i++) { - uintptr_t base; + uint64_t base; unsigned int index; index = fixed_set_resources[i].index; @@ -83,8 +83,9 @@ void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, return; base = fixed_set_resources[i].base; - - pci_write_config32(SA_DEV_ROOT, index, base | 1); + if (base >> 32) + pci_write_config32(SA_DEV_ROOT, index + 4, base >> 32); + pci_write_config32(SA_DEV_ROOT, index, (base & 0xffffffff) | 1); } } @@ -99,12 +100,14 @@ void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, int i; for (i = 0; i < count; i++) { - uintptr_t base; + uint64_t base; unsigned int index; base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; - write32((void *)(MCH_BASE_ADDRESS + index), base | 1); + if (base >> 32) + write32((void *)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32((void *)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); } } |